Semiconductor package
A semiconductor package is provided. A semiconductor package includes a wiring structure, which includes a first insulating layer and a first wiring pad inside the first insulating layer a semiconductor chip on the wiring structure, an interposer having one surface facing the semiconductor chip and including a second insulating layer and a second wiring pad inside the second insulating layer, a connecting member connecting the first wiring pad and the second wiring pad, a support member in the first recess and between the wiring structure and the interposer, and a mold layer covering the semiconductor chip. One surface of the wiring structure includes a first recess exposing at least a part of the first insulating layer.
1 . A semiconductor package comprising:
a wiring structure including a first insulating layer and a first wiring pad in the first insulating layer, one surface of the wiring structure including a first recess exposing at least a part of the first insulating layer;
a semiconductor chip on the wiring structure;
an interposer having one surface facing the semiconductor chip, the interposer including a second insulating layer and a second wiring pad in the second insulating layer;
a connecting member connecting the first wiring pad to the second wiring pad;
a support member in the first recess and between the wiring structure and the interposer; and
a mold layer covering the semiconductor chip,
wherein a thickness of the support member in the first recess is thicker than a distance between the one surface of the wiring structure and the one surface of the interposer, and
the support member includes an insulating material.
2 . The semiconductor package of claim 1 , wherein the mold layer fills the first recess.
3 . The semiconductor package of claim 1 , wherein a width of the first recess is greater than a width of the support member.
4 . The semiconductor package of claim 1 , wherein
the one surface of the interposer includes a second recess that exposes at least a part of the second insulating layer, and
the support member extends into the second recess.
5 . The semiconductor package of claim 1 , wherein
a first surface of the support member is on the one surface of the wiring structure,
a second surface of the support member faces the first surface,
the second surface of the support member is on the one surface of the interposer, and
the wiring structure further includes a support pattern that supports the support member below the first surface.
6 . The semiconductor package of claim 1 , wherein
the wiring structure further includes a support pattern that supports the support member in the first recess, and at least part of an upper surface of the support pattern comes into contact with the mold layer.
7 . The semiconductor package of claim 5 , wherein the support pattern is buried in the first insulating layer and does not come into contact with the mold layer.
8 . The semiconductor package of claim 5 , wherein
the support pattern is not electrically connected to a connecting structure placed below the wiring structure.
9 . A semiconductor package comprising:
a first wiring structure including a first insulating layer and a first wiring pad in the first insulating layer;
a semiconductor chip on the first wiring structure;
a second wiring structure including a second insulating layer facing the semiconductor chip and a second wiring pad in the second insulating layer;
a support member between the first wiring structure and the second wiring structure; and
a mold layer covering the semiconductor chip,
wherein one surface of the first wiring structure includes a first recess having a side wall and a bottom surface,
the side wall of the first recess exposes at least a part of the first insulating layer,
the bottom surface of the first recess is connected to the side wall and formed on the one surface of the first wiring structure,
the support member extends into the first recess,
a thickness of the support member in the first recess being thicker than a distance between the one surface of the first wiring structure and one surface of the second wiring structure, and
the support member includes an insulating material.
10 . The semiconductor package of claim 9 , wherein the mold layer is on the side wall and the bottom surface of the first recess.
11 . The semiconductor package of claim 9 , wherein a width of the first recess is greater than a width of the support member.
12 . The semiconductor package of claim 9 , wherein
the one surface of the second wiring structure includes a second recess that exposes at least a part of the second insulating layer, and
the support member extends into the second recess.
13 . The semiconductor package of claim 9 , wherein
a first surface of the support member is on the one surface of the first wiring structure,
a second surface of the support member is on the one surface of the second wiring structure, and
the first wiring structure further includes a support pattern that supports the support member below the first surface of the support member.
14 . A semiconductor package comprising:
a first semiconductor package including a wiring structure, a semiconductor chip, an interposer, a connecting member, and a plurality of support members,
the wiring structure including a first insulating layer and a first wiring pad in the first insulating layer,
one surface of the wiring structure including a first recess exposing at least a part of the first insulating layer,
the semiconductor chip mounted on the wiring structure,
the interposer having one surface face the semiconductor chip,
the interposer including a second insulating layer and a second wiring pad in the second insulating layer,
the connecting member connecting the first wiring pad and the second wiring pad, and
at least one of the plurality of support members extending between the wiring structure and the interposer,
wherein a thickness of the at least one of the plurality of support members in the first recess is thicker than a distance between the one surface of the wiring structure and the one surface of the interposer,
the at least one of the plurality of support members and the connecting member are different from each other,
the at least one of the plurality of support members in the first recess is arranged between the semiconductor chip and the connecting member, and
the semiconductor chip is disposed between the plurality of support members.
15 . The semiconductor package of claim 14 , further comprising:
a second semiconductor package placed on the first semiconductor package.
16 . The semiconductor package of claim 14 , comprising:
a mold layer covering the semiconductor chip,
wherein the mold layer fills the first recess.
17 . The semiconductor package of claim 14 , wherein
the one surface of the interposer includes a second recess that exposes at least a part of the second insulating layer, and
the at least one of the plurality of support members extends into the second recess.