Semiconductor device

1 . A semiconductor device, comprising:

a wiring layer having a wiring surface;

a semiconductor chip stacked in a defined region on a the wiring surface; and

a signal line wired on the wiring surface and crossing at least one boundary line of the stacked semiconductor chip,

wherein an angle formed between the signal line and the boundary line at the crossing is less than a reference angle,

wherein the signal line includes a plurality of segments,

wherein at least one segment intersects the boundary line at an endpoint located on the boundary line and forms an angle with respect to the boundary line that is less than the reference angle,

wherein adjacent segments of the plurality of segments form a non-zero angle with each other, and wherein no pair of adjacent segments is collinear.

2 . The semiconductor device according to claim 1 , wherein

each segment that intersects the boundary line forms an angle with the boundary line that is, less than the reference angle.

3 . The semiconductor device according to claim 1 , wherein

the signal line first segment that forms an angle the boundary line less than the reference angle, and

a width of the first segment is greater than a width of at least one other segment of the signal line.

4 . The semiconductor device according to claim 1 , wherein

each segment located within a predetermined distance from the boundary line forms an angle with the boundary line that is less than the reference angle.

5 . The semiconductor device according to claim 1 , wherein

the signal line connects a pair of terminals, and

a redundant signal line connecting the pair of terminals along a different wiring path is further provided in the wiring layer.

6 . The semiconductor device according to claim 5 , wherein the signal line is wired through a via located on the boundary line.

7 . The semiconductor device according to claim 1 , further comprising

a dielectric layer;

an external terminal disposed on the dielectric layer;

a conductive member having opposed first and second surfaces;

and a seed layer,

wherein the first surface of the conductive member is connected to the external terminal, and

wherein the second surface of the conductive member includes a first region in contact with the dielectric layer and a second region not in contact with the seed layer.

8 . The semiconductor device according to claim 7 , wherein an end surface of the conductive member is tapered.

9 . The semiconductor device according to claim 7 , wherein the conductive member includes a plurality of lands and linear lines.

10 . The semiconductor device according to claim 1 , wherein the wiring layer includes

a signal line region in which the signal line is wired, and

a power supply ground region configured to supply power voltage or a ground to the semiconductor chip.

11 . The semiconductor device according to claim 10 , wherein at least one of a power supply line or a ground line in the power supply ground region is formed as a mesh pattern.

12 . The semiconductor device according to claim 10 , wherein the power supply ground region includes a solid conductive pattern.

13 . The semiconductor device according to claim 10 , wherein an angle formed between a boundary separating the signal line region and the power supply ground region and the boundary line is not equal to 90 degrees.

14 . The semiconductor device according to claim 1 , wherein the wiring layer and the semiconductor chip are included in a wafer level chip size package (WCSP).

15 . The semiconductor device according to claim 1 , wherein the wiring layer and the semiconductor chip are includes in a fine pitch ball grid array (FBGA) package.

16 . The semiconductor device according to claim 1 , wherein the wiring layer is formed in an interposer substrate.

17 . A semiconductor device, comprising:

a wiring layer having a wiring surface;

a semiconductor chip stacked in a defined region on the wiring surface; and

a signal line wired on the wiring surface and crossing at least one boundary line of the stacked semiconductor chip,

wherein an angle formed between the signal line and the boundary line at the crossing is less than a reference angle,

wherein the signal line includes a plurality of segments,

wherein the plurality of segments includes three segments,

wherein at least one segment intersects the boundary line at an endpoint located on the boundary line and forms an angle with respect to the boundary line that is less than the reference angle,

wherein adjacent segments of the plurality of segments form a non-zero angle with each other, and

wherein no pair of adjacent segments is collinear.

18 . The semiconductor device according to claim 17 , wherein each segment that intersects the boundary line forms an angle with the boundary line that is less than the reference angle.

19 . A semiconductor device, comprising:

a wiring layer having a wiring surface;

a semiconductor chip stacked in a defined region on the wiring surface; and

a signal line wired on the wiring surface and crossing at least one boundary line of the stacked semiconductor chip,

wherein an angle formed between the signal line and the boundary line at the crossing is less than a reference angle,

wherein the reference angle is 50 degrees,

wherein the signal line includes a plurality of segments,

wherein the plurality of segments includes three segments,

wherein at least one segment intersects the boundary line at an endpoint located on the boundary line and forms an angle with respect to the boundary line that is less than the reference angle,

wherein adjacent segments of the plurality of segments form a non-zero angle with each other, and

wherein no pair of adjacent segments is collinear.

20 . The semiconductor device according to claim 18 , wherein each segment that intersects the boundary line forms an angle with the boundary line that is less than the reference angle.