Semiconductor device assemblies with cavity-embedded cubes and logic-supporting interposers

1 . A semiconductor device assembly, comprising:

a package substrate including:

an upper surface having a plurality of internal contacts,

a lower surface having a plurality of external contacts electrically coupled to the plurality of internal contacts, and

a cavity extending into the package substrate from the upper surface, wherein the plurality of internal contacts of the upper surface are spaced laterally away from the cavity;

a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack of first semiconductor devices having a plurality of stack contacts substantially coplanar with the plurality of internal contacts;

an interposer disposed over the upper surface of the package substrate, over the uppermost first semiconductor device, and over the cavity, the interposer including:

a bottom surface having a first plurality of lower contacts electrically coupled to the plurality of stack contacts and a second plurality of lower contacts electrically coupled to the plurality of internal contacts, and

a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts;

a second semiconductor device disposed over the top surface of the interposer and including a plurality of die contacts electrically coupled to the plurality of upper contacts; and

an encapsulant material that at least partially encapsulates the interposer and the second semiconductor device, a bottom surface of the encapsulant material being in contact with the upper surface of the package substrate.

2 . The semiconductor device assembly of claim 1 , wherein the package substrate is a printed circuit board.

3 . The semiconductor device assembly of claim 1 , wherein the interposer is a printed circuit board.

4 . The semiconductor device assembly of claim 1 , wherein the first semiconductor devices are memory dies and wherein the second semiconductor device is a memory controller configured to manage the memory dies.

5 . The semiconductor device assembly of claim 1 , further comprising a wireless interconnect structure disposed at a sidewall of the cavity and configured to communicate with a lower first semiconductor device of the stack of first semiconductor devices.

6 . The semiconductor device assembly of claim 5 , wherein the wireless interconnect structure is coupled to an internal contact of the plurality of internal contacts or to an external contact of the plurality of external contacts through a configurable fuse array.

7 . The semiconductor device assembly of claim 1 , wherein:

the cavity is a first cavity,

the plurality of stack contacts is a first plurality of stack contacts,

the package substrate further includes a second cavity extending into the package substrate from the upper surface,

the semiconductor device assembly further comprises a stack of third semiconductor devices disposed in the second cavity, an uppermost third semiconductor device of the stack of third semiconductor devices having a second plurality of stack contacts substantially coplanar with the plurality of internal contacts, and

the bottom surface of the interposer includes a third plurality of lower contacts electrically coupled to the second plurality of stack contacts.

8 . The semiconductor device assembly of claim 1 , further comprising a thermally conductive lid disposed over the encapsulant material.

9 . A semiconductor device assembly, comprising:

a package substrate including:

an upper surface having a plurality of internal contacts,

a lower surface having a plurality of external contacts electrically coupled to the plurality of internal contacts, and

a plurality of cavities extending into the package substrate from the upper surface, wherein the plurality of internal contacts of the upper surface are spaced laterally away from the plurality of cavities;

a plurality of stacks of first semiconductor devices, each stack of the plurality of stacks of first semiconductor devices being disposed in a corresponding cavity of the plurality of cavities, an uppermost first semiconductor device of each stack having a plurality of stack contacts substantially coplanar with the plurality of internal contacts;

an interposer disposed over the upper surface of the package substrate, over the uppermost first semiconductor device of each stack, and over the cavity plurality of cavities, the interposer including:

a bottom surface having a first plurality of lower contacts electrically coupled to the plurality of stack contacts of each of the plurality of stacks of first semiconductor devices and a second plurality of lower contacts electrically coupled to the plurality of internal contacts, and

a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts;

a second semiconductor device disposed over the top surface of the interposer and including a plurality of die contacts electrically coupled to the plurality of upper contacts; and

an encapsulant material that at least partially encapsulates the interposer and the second semiconductor device, a bottom surface of the encapsulant material being in contact with the upper surface of the package substrate.

10 . The semiconductor device assembly of claim 9 , wherein the package substrate is a printed circuit board.

11 . The semiconductor device assembly of claim 9 , wherein the interposer is a printed circuit board.

12 . The semiconductor device assembly of claim 9 , wherein the first semiconductor devices are memory dies and wherein the second semiconductor device is a memory controller configured to manage the memory dies.

13 . The semiconductor device assembly of claim 9 , further comprising a wireless interconnect structure disposed at a sidewall of each of the plurality of cavities and configured to communicate with a lower first semiconductor device of the corresponding stack.

14 . The semiconductor device assembly of claim 13 , wherein each wireless interconnect structure is coupled to an internal contact of the plurality of internal contacts or to an external contact of the plurality of external contacts through a configurable fuse array.

15 . The semiconductor device assembly of claim 9 , further comprising a thermally conductive lid disposed over the encapsulant material.

16 . A method of making a semiconductor device assembly, comprising:

providing a package substrate including an upper surface having a plurality of internal contacts, a lower surface having a plurality of external contacts electrically coupled to the plurality of internal contacts, and a cavity extending into the package substrate from the upper surface, wherein the plurality of internal contacts of the upper surface are spaced laterally away from the cavity;

disposing a stack of first semiconductor devices in the cavity, an uppermost first semiconductor device of the stack of first semiconductor devices having a plurality of stack contacts substantially coplanar with the plurality of internal contacts;

disposing an interposer over the upper surface of the package substrate, over the uppermost first semiconductor device, and over the cavity, the interposer including (i) a bottom surface having a first plurality of lower contacts and a second plurality of lower contacts and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts;

electrically coupling the first plurality of lower contacts to the plurality of internal contacts and the second plurality of lower contacts to the plurality of stack contacts;

disposing a second semiconductor device over the top surface of the interposer;

electrically coupling a plurality of die contacts of the second semiconductor device to the plurality of upper contacts of the interposer; and

at least partially encapsulating the interposer and the second semiconductor device with an encapsulant material, a bottom surface of the encapsulant material being in contact with the upper surface of the package substrate.

17 . The method of claim 16 , further comprising attaching a thermally conductive lid to the encapsulant material.