Semiconductor package
A semiconductor package includes a first semiconductor chip on a package substrate, a second semiconductor chip on the first semiconductor chip and having a redistribution layer on a bottom surface thereof, under-bump pads on a bottom surface of the redistribution layer, first solders adjacent to the first semiconductor chip and connecting first pads of the under-bump pads to substrate pads of the package substrate, and a molding layer on the package substrate and covering the first and second semiconductor chips and the first solders. Second pads of the under-bump pads are in direct contact with a top surface of the first semiconductor chip. The first pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip. The second pads are insulated from the integrated circuit of the second semiconductor chip.
1 . A semiconductor package, comprising:
a first semiconductor chip on a package substrate;
a second semiconductor chip on the first semiconductor chip;
a redistribution layer on a bottom surface of the second semiconductor chip;
a plurality of under-bump pads on a bottom surface of the redistribution layer;
a plurality of first solders adjacent to the first semiconductor chip, the plurality of first solders connecting a plurality of first pads of the plurality of under-bump pads to a plurality of substrate pads of the package substrate; and
a molding layer on the package substrate, wherein
the molding layer covers the first semiconductor chip, the second semiconductor chip, and the plurality of first solders,
a plurality of second pads of the plurality of under-bump pads are in direct contact with a top surface of the first semiconductor chip,
the plurality of first pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip,
the plurality of second pads are insulated from the integrated circuit of the second semiconductor chip,
the molding layer is between the first semiconductor chip and the second semiconductor chip, and
lateral surfaces of the plurality of second pads are in direct contact with the molding layer and bottom surfaces of the plurality of second pads are in direct contact with the top surface of the first semiconductor chip.
2 . The semiconductor package of claim 1 , wherein the redistribution layer includes:
a dielectric pattern that covers the bottom surface of the second semiconductor chip and a plurality of first chip pads of the second semiconductor chip; and
a wiring pattern in the dielectric pattern, the wiring pattern being coupled to the plurality of first chip pads and electrically connected to the integrated circuit of the second semiconductor chip,
wherein the plurality of first pads penetrate the dielectric pattern and are coupled to the wiring pattern.
3 . The semiconductor package of claim 2 , wherein the dielectric pattern separates the plurality of second pads from the wiring pattern.
4 . The semiconductor package of claim 1 , wherein
the plurality of first pads are spaced apart from the first semiconductor chip when viewed in a plan view, and
the plurality of second pads vertically overlap the first semiconductor chip.
5 . The semiconductor package of claim 1 , wherein the first semiconductor chip is coupled to the package substrate through a plurality of second solders on a plurality of second chip pads, the plurality of second chip pads being on a bottom surface of the first semiconductor chip.
6 . The semiconductor package of claim 5 , wherein a first height of the plurality of first solders is about 1.5 times to about 30 times a second height of the plurality of second solders.
7 . The semiconductor package of claim 6 , wherein
the first height of the plurality of first solders is in a range of about 50 μm to about 300 μm, and
the second height of the plurality of second solders is in a range of about 10 μm to about 50 μm.
8 . The semiconductor package of claim 1 , wherein bottom surfaces of the plurality of first pads and the bottom surfaces of the plurality of second pads are at a same level from the bottom surface of the second semiconductor chip.
9 . The semiconductor package of claim 1 , wherein
the first semiconductor chip has a first lateral surface in a first direction and a second lateral surface in a second direction that intersects the first direction, the first lateral surface and the second lateral surface being in direct contact with each other, and
when viewed in a plan view, the second semiconductor chip protrudes beyond the first lateral surface and does not protrude beyond the second lateral surface.
10 . The semiconductor package of claim 9 , wherein
a wiring pattern of the redistribution layer is connected to the integrated circuit of the second semiconductor chip in a window region on a top surface of the redistribution layer,
the window region extends in the second direction on a central portion of the redistribution layer, and
the plurality of first pads are arranged along the second direction on one side in the first direction from the window region.
11 . The semiconductor package of claim 1 , wherein
the first semiconductor chip has a first lateral surface in a first direction and a second lateral surface in a second direction that intersects the first direction, the first lateral surface and the second lateral surface being in direct contact with each other, and
when viewed in a plan view, the second semiconductor chip protrudes beyond both of the first lateral surface and the second lateral surface.
12 . A semiconductor package, comprising:
a package substrate;
a first semiconductor chip and a second semiconductor chip that are sequentially stacked on the package substrate;
a redistribution layer on a bottom surface of the second semiconductor chip;
a plurality of first pads on a bottom surface of the redistribution layer, and between the second semiconductor chip and the first semiconductor chip;
a molding layer on the package substrate, the molding layer covering the first semiconductor chip and the second semiconductor chip; and
a plurality of external terminals on a bottom surface of the package substrate, wherein
the second semiconductor chip is offset from the first semiconductor chip in a horizontal direction that is parallel to at least a top surface of the package substrate to vertically overlap a first lateral surface and a second lateral surface of the first semiconductor chip, the first lateral surface and the second lateral surface being adjacent to each other,
the first semiconductor chip is on the package substrate through a plurality of first solders on a bottom surface of the first semiconductor chip such that the plurality of first solders are between the first semiconductor chip and the package substrate,
the second semiconductor chip is on the package substrate through a plurality of second solders on the package substrate such that the plurality of second solders are between the second semiconductor chip and the package substrate, the plurality of second solders being adjacent to the first lateral surface and the second lateral surface of the first semiconductor chip and being spaced apart from the first semiconductor chip,
the second semiconductor chip is supported on a top surface of the first semiconductor chip,
the molding layer is between the first semiconductor chip and the second semiconductor chip, and
lateral surfaces of the plurality of first pads are in direct contact with the molding layer and bottom surfaces of the plurality of first pads are in direct contact with the top surface of the first semiconductor chip.
13 . The semiconductor package of claim 12 , further comprising:
a plurality of second pads on the bottom surface of the redistribution layer, and
wherein the plurality of second pads are adjacent to the first semiconductor chip and are connected through the plurality of second solders to the package substrate.
14 . The semiconductor package of claim 13 , wherein the bottom surfaces of the plurality of first pads and bottom surfaces of the plurality of second pads are at a same level from the bottom surface of the second semiconductor chip.
15 . The semiconductor package of claim 13 , wherein
the plurality of second pads are spaced apart from the first semiconductor chip when viewed in a plan view, and
the plurality of first pads vertically overlap the first semiconductor chip.
16 . The semiconductor package of claim 13 , wherein
the plurality of second pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip, and
the plurality of first pads are insulated from the integrated circuit of the second semiconductor chip.
17 . A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate;
a second semiconductor chip on the first semiconductor chip and horizontally offset from the first semiconductor chip in a horizontal direction that is parallel to at least a top surface of the substrate;
a redistribution layer on a bottom surface of the second semiconductor chip and connected to an integrated circuit of the second semiconductor chip;
a dummy pad between the first semiconductor chip and the second semiconductor chip and on a bottom surface of the redistribution layer;
a signal pad on one side of the first semiconductor chip and on the bottom surface of the redistribution layer;
a connection terminal on the one side of the first semiconductor chip and between the substrate and the second semiconductor chip; and
a molding layer on the substrate and covering the first semiconductor chip and the second semiconductor chip, wherein
the molding layer fills both a space between the substrate and the first semiconductor chip and a space between the substrate and the second semiconductor chip,
the molding layer is between the first semiconductor chip and the second semiconductor chip,
the connection terminal directly connects the signal pad to a substrate pad of the substrate, and
lateral surfaces of the dummy pad are in direct contact with the molding layer and bottom surfaces of the dummy pad are in direct contact with a top surface of the first semiconductor chip.
18 . The semiconductor package of claim 17 , wherein the second semiconductor chip is shifted from the first semiconductor chip to vertically overlap a first lateral surface and a second lateral surface of the first semiconductor chip, the first lateral surface and the second lateral surface being adjacent to each other.
19 . The semiconductor package of claim 17 , wherein a bottom surface of the dummy pad and a bottom surface of the signal pad are at a same level from the bottom surface of the second semiconductor chip.
20 . The semiconductor package of claim 17 , wherein
the signal pad is connected through the redistribution layer to the integrated circuit of the second semiconductor chip, and
the dummy pad is insulated from the integrated circuit of the second semiconductor chip.