Connecting semiconductor dies through traces
This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.
1 . A semiconductor device assembly, comprising:
a first semiconductor die including a first layer of a dielectric material at which first circuitry is disposed, the first layer having a first upper surface;
a second semiconductor die including a second layer of the dielectric material at which second circuitry is disposed, the second layer having a second upper surface; and
one or more traces extending from a first side surface of the first layer and a second side surface of the second layer, the one or more traces directly coupling the first circuitry and the second circuitry, wherein the first side surface is orthogonal to the first upper surface, and wherein the second side surface is orthogonal to the second upper surface.
2 . The semiconductor device assembly of claim 1 , wherein the one or more traces are not surrounded by the dielectric material.
3 . The semiconductor device assembly of claim 1 , wherein the second semiconductor die is mounted on the first semiconductor die such that the one or more traces form an arc.
4 . The semiconductor device assembly of claim 1 , further comprising:
a third semiconductor die including a third layer of the dielectric material at which third circuitry is disposed; and
one or more additional traces extending from a third side surface of the second layer and a fourth side surface of the third layer, the one or more additional traces directly coupling the second circuitry and the third circuitry.
5 . The semiconductor device assembly of claim 4 , wherein:
the one or more traces have a first length; and
the one or more additional traces have a second length that is greater than the first length.
6 . The semiconductor device assembly of claim 1 , wherein the one or more traces extend from a first position on the first side surface a from non-zero distance from the first upper surface of the first layer, and extend from a second position on the second upper surface a second non-zero distance from the second upper surface of the second layer.
7 . The semiconductor device assembly of claim 1 , wherein:
the first circuitry is embedded in the first layer; and
the second circuitry is embedded in the second layer.
8 . A semiconductor device assembly, comprising:
a first semiconductor die including a first active side at which first circuitry is disposed and a first inactive side opposite the first active side;
a second semiconductor die including a second active side at which second circuitry is disposed and a second inactive side opposite the second active side; and
a third semiconductor die including a third active side at which third circuitry is disposed and a third inactive side opposite the third active side,
wherein the first active side is physically coupled to the second active side and the second inactive side is physically coupled to the third inactive side,
wherein the first circuitry is electrically coupled to the second circuitry via one or more traces extending between a first sidewall of the first semiconductor die at the first active side and a second sidewall of the second semiconductor die at the second active side, wherein the first sidewall is orthogonal to a first plane of the first active side, and wherein the second sidewall is orthogonal to a second plane of the second active side, and
wherein the first circuitry, the second circuitry, and the third circuitry are electrically coupled exclusive of any through-silicon vias (TSV).
9 . The semiconductor device assembly of claim 8 wherein the one or more traces are one or more first traces, and wherein the semiconductor device assembly further comprises:
one or more second traces coupling the second circuitry and the third circuitry.
10 . The semiconductor device assembly of claim 9 , wherein:
the one or more second traces extend between the second sidewall of the second semiconductor die at the second active side and a third sidewall of the third semiconductor die at the third active side to electrically couple the second circuitry and the third circuitry.
11 . The semiconductor device assembly of claim 10 , wherein:
the one or more traces extend between the first sidewall and the second sidewall such that the one or more traces are configured in a first arc shape having a first radius of curvature; and
the one or more second traces extend between the second sidewall and the third sidewall such that the one or more second traces are configured in a second arc shape having a second radius of curvature greater than the first radius of curvature.
12 . The semiconductor device assembly of claim 9 , wherein:
the one or more first traces have a first length; and
the one or more second traces have a second length greater than the first length.
13 . The semiconductor device assembly of claim 8 , further comprising an encapsulant that at least partially encapsulates the first semiconductor die, the second semiconductor die, and the third semiconductor die.
14 . The semiconductor device assembly of claim 8 , wherein the third semiconductor die further includes one or more contact pads coupled to the third circuitry and disposed at the third active side, the semiconductor device assembly further comprising:
a substrate coupled to the one or more contact pads at the third active side effective to electrically couple the substrate to the first circuitry, the second circuitry, and the third circuitry.