IP Library › Granted Patent US 12666991

Granted Patent B2

US 12666991 · App. 17/855,189 · Granted Jun 23, 2026

Integrated device comprising pillar interconnects with variable widths

Inventors: Wei Wang (San Diego, CA); Dongming He (San Diego, CA); Yangyang Sun (San Diego, CA); Wei Hu (San Diego, CA)

Assignee: QUALCOMM INCORPORATED

H10W72/20 H10W72/012 H10W72/01235 H10W72/072 H10W72/07236 H10W72/222 H10W72/234 H10W72/242 H10W72/29 H10W72/90 H10W72/923 H10W72/934 H10W72/9415 H10W90/724

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Quick Facts

Patent No.: US 12666991
App. No.: 17/855,189
Granted: Jun 23, 2026
Kind: B2

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Abstract

An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

Claims (82)

1 . An integrated device comprising:

a die portion comprising:

a plurality of pads comprising a first pad;

a first passivation layer coupled to and touching the plurality of pads;

a second passivation layer coupled to and touching the first passivation layer, wherein the second passivation layer is different from the first passivation layer; and

a plurality of under bump metallization interconnects coupled to the plurality of pads, wherein the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect that is coupled to and touching the first pad; and

a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, wherein the plurality of pillar interconnects includes a first pillar interconnect that is coupled to and touching the first under bump metallization interconnect, wherein the first pillar interconnect comprises:

a first width that corresponds to a widest part of the first pillar interconnect; and

a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width,

wherein the first pillar interconnect includes a profile cross section that includes (i) a first trapezoid shape and (ii) a second trapezoid shape that is coupled to and touching the first trapezoid shape,

wherein the second trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape,

wherein the first trapezoid shape touches the first under bump metallization interconnect from the plurality of under bump metallization interconnects, and

wherein the second width is a width of a part of the second trapezoid shape that is vertically farthest away from the first under bump metallization interconnect.

2 . The integrated device of claim 1 ,

wherein the first pillar interconnect includes a diagonal surface,

wherein the first passivation layer includes a hard passivation layer, and

wherein the second passivation layer includes a polymer passivation layer.

3 . The integrated device of claim 1 , wherein the first pillar interconnect includes a surface that includes a step surface.

4 . The integrated device of claim 1 ,

wherein the first pillar interconnect includes the profile cross section that further includes a third trapezoid shape that is coupled to and touching the second trapezoid shape such that the second trapezoid shape is located between the first trapezoid shape the third trapezoid shape, and

wherein the third trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape.

5 . The integrated device of claim 4 , wherein the first pillar interconnect includes the profile cross section that further includes a fourth trapezoid shape that is coupled to and touching the third trapezoid shape.

6 . The integrated device of claim 1 , wherein a portion of the second trapezoid shape touches the first under bump metallization interconnect.

7 . The integrated device of claim 6 , wherein the second trapezoid shape includes a first portion that has the first width and a second portion that has the second width.

8 . The integrated device of claim 1 , wherein the first pillar interconnect includes a first diagonal surface with a first angle and a second diagonal surface with a second angle.

9 . The integrated device of claim 1 , wherein the die portion comprises:

a die substrate;

a plurality of transistors formed in and/or over the die substrate; and

an interconnect portion located over the die substrate.

10 . A package comprising:

a substrate; and

an integrated device comprising:

a plurality of pad interconnects comprising a first pad;

a plurality of under bump metallization interconnects comprising a first under bump metallization interconnect that is coupled to and touching the first pad; and

a plurality of pillar interconnects comprising a first pillar interconnect,

wherein the first pillar interconnect is coupled to and touching the first under bump metallization interconnect, and

wherein the first pillar interconnect comprises:

a first width that corresponds to a widest part of the first pillar interconnect; and

wherein the integrated device is coupled to the substrate through the plurality of pillar interconnects and the plurality of solder interconnects,

wherein the second trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape,

wherein the first trapezoid shape touches the first under bump metallization interconnect from the plurality of under bump metallization interconnects, and

wherein the second width is a width of a part of the second trapezoid shape that is vertically farthest away from the first under bump metallization interconnect.

11 . The package of claim 10 ,

wherein the integrated device further comprises:

a first passivation layer coupled to and touching the plurality of pads; and

a second passivation layer coupled to and touching the first passivation layer,

wherein the first passivation layer includes a hard passivation layer, and

wherein the second passivation layer includes a polymer passivation layer, and

wherein the first pillar interconnect includes a diagonal surface.

12 . The package of claim 10 , wherein the first pillar interconnect includes a surface that includes a step surface.

13 . The package of claim 10 ,

wherein the third trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape.

14 . The package of claim 13 , wherein the first pillar interconnect includes the profile cross section that further includes a fourth trapezoid shape that is coupled to and touching the third trapezoid shape.

15 . The package of claim 10 , wherein a portion of the second trapezoid shape touches the first under bump metallization interconnect.

16 . The package of claim 15 , wherein the second trapezoid shape includes a first portion that has the first width and a second portion that has the second width.

17 . The package of claim 10 , wherein the first pillar interconnect includes a first diagonal surface with a first angle and a second diagonal surface with a second angle.

18 . The package of claim 10 , wherein the package is part of a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IOT) device, and a device in an automotive vehicle.

19 . A method for fabricating an integrated device, comprising:

providing a die portion comprising:

a plurality of pads comprising a first pad;

a first passivation layer coupled to and touching the plurality of pads;

a second passivation layer coupled to and touching the first passivation layer, wherein the second passivation layer is different from the first passivation layer; and

a plurality of under bump metallization interconnects coupled to the plurality of pads, wherein the plurality of under bump metallization interconnects comprise a first under bump metallization interconnect that is coupled to and touching the first pad; and

forming a plurality of pillar interconnects over the plurality of under bump metallization interconnects,

wherein forming the plurality of pillar interconnects comprises forming a first pillar interconnect that is coupled to and touching the first under bump metallization interconnect,

wherein the first pillar interconnect comprises:

a first width that corresponds to a widest part of the first pillar interconnect; and

wherein the second trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape,

wherein the first trapezoid shape touches the first under bump metallization interconnect from the plurality of under bump metallization interconnects, and

wherein the second width is a width of a part of the second trapezoid shape that is vertically farthest away from the first under bump metallization interconnect.

20 . The method of claim 19 ,

wherein forming the first pillar interconnect comprises forming the first pillar interconnect such that the first pillar interconnect includes a diagonal surface,

wherein the first passivation layer includes a hard passivation layer, and

wherein the second passivation layer includes a polymer passivation layer.

21 . The method of claim 19 ,

wherein forming the first pillar interconnect comprises forming the first pillar interconnect such that the profile cross section of the first pillar interconnect further includes a third trapezoid shape that is coupled to and touching the second trapezoid shape such that the second trapezoid shape is located between the first trapezoid shape the third trapezoid shape, and wherein the third trapezoid shape is an inverted trapezoid shape relative to the first trapezoid shape.

22 . The method of claim 21 , wherein forming the plurality of pillar interconnects comprises further forming a second pillar interconnect such that the second pillar interconnect comprises a profile cross section that includes (i) another first trapezoid shape and (ii) another second trapezoid shape that is coupled to and touching the another first trapezoid shape, wherein the another second trapezoid shape is an inverted trapezoid shape relative to the another first trapezoid shape.