Package structure
Examples of the present disclosure provide a package structure, the package structure including: a package substrate; a semiconductor device on the package substrate; and a molding layer over the semiconductor device, the molding layer having a plurality of grooves disposed at its surface.
1 . A package structure, comprising:
a package substrate;
a semiconductor device on the package substrate;
a molding layer over the semiconductor device, the molding layer including a plurality of grooves disposed at its surface; and
independent patch structures selectively insertable or removable from the plurality of grooves, wherein a portion of the independent patch structures are insertable into a subset of the plurality of grooves.
2 . The package structure of claim 1 , further comprising an independent patch structure of the independent patch structures being located in each one of the grooves.
3 . The package structure of claim 2 , wherein the independent patch structure has a coefficient of thermal expansion greater than that of the molding layer.
4 . The package structure of claim 3 , wherein the independent patch structure comprises at least one of:
resin, glue or copper.
5 . The package structure of claim 2 , wherein the independent patch structure has a coefficient of thermal expansion smaller than that of the molding layer.
6 . The package structure of claim 5 , wherein the independent patch structure comprises silicon.
7 . The package structure of claim 2 , wherein at least two of the independent patch structures have different coefficients of thermal expansion or have different densities.
8 . The package structure of claim 2 , wherein a thermal conductivity of the independent patch structure is greater than a preset value.
9 . The package structure of claim 8 , wherein the preset value is 160 Watts (W)/milli-Kelvin (mK).
10 . The package structure of claim 2 , wherein a contour of the independent patch structure has a same shape as a contour of at least one of the grooves.
11 . The package structure of claim 2 , wherein a dimension of the independent patch structure is larger than that of a corresponding portion of at least one of the grooves.
12 . The package structure of claim 2 , wherein a contour of the independent patch structure has a shape of at least one of:
a cylinder, a circular cone, a triangular pyramid, a hemisphere or a cube.
13 . The package structure of claim 1 , wherein the semiconductor device comprises a three-dimensional NAND memory.
14 . The package structure of claim 1 , wherein the independent patch structures comprise pre-formed components formed according to dimensions of the plurality of grooves.
15 . The package structure of claim 1 , wherein the independent patch structures are formed separate from the molding layer and inserted in finished form into the molding layer.
16 . The package structure of claim 1 , wherein a first portion of the independent patch structures has a first coefficient of thermal expansion and a second portion of the independent patch structures has a second coefficient of thermal expansion.
17 . The package structure of claim 16 wherein the first coefficient of thermal expansion is greater than that of the molding layer, and wherein the second coefficient of thermal expansion is greater than that of the molding layer.
18 . The package structure of claim 1 , wherein fewer than all of the plurality of grooves are filled with the independent patch structures, and wherein a location of the plurality of grooves which are filled with the independent patch structures corresponds to locations of warpage of the package substrate.
19 . The package structure of claim 1 , wherein the package structure has a non-zero amount of warpage, and wherein the independent patch structures are placed into the subset of the plurality of grooves in locations configured to reduce the amount of warpage of the package structure.
20 . The package structure of claim 19 , wherein a material of a respective one of the independent patch structures filling a corresponding one of the plurality of grooves is selected according to the amount of warpage of the package structure corresponding to a location of the one of the plurality of grooves.