Semiconductor device that uses bonding layer to join semiconductor substrates together
Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.
1 . A semiconductor device comprising:
a first interconnection structure adjacent to a first semiconductor substrate, wherein the first interconnection structure is in physical contact with a first gate contact, the first gate contact having straight sidewalls from a top of the first gate contact to a bottom of the first gate contact;
a first bonding layer in physical contact with the first interconnection structure, wherein the first bonding layer has a first bonding interface on a first side of the first bonding layer;
a second interconnection structure adjacent to a second semiconductor substrate, wherein the second interconnection structure is bonded to the first bonding layer at the first bonding layer;
through vias extending through the second semiconductor substrate, wherein each of the through vias that extends through the second semiconductor substrate makes physical contact with a conductive portion of the second interconnection structure;
an encapsulant surrounding the second semiconductor substrate and a third semiconductor substrate;
through encapsulant vias extending from a first side of the encapsulant to a second side of the encapsulant, the through encapsulant vias having a first height as large as a maximum height of the encapsulant; and
a third interconnection structure extending fully over the second semiconductor substrate.
2 . The semiconductor device of claim 1 , wherein the first gate contact has a first width of between about 1 nm and about 180 nm.
3 . The semiconductor device of claim 1 , wherein the first gate contact has a first width of between about 1 nm and about 5 nm.
4 . The semiconductor device of claim 1 , wherein the first semiconductor 4 . substrate is part of an unfinished wafer.
5 . The semiconductor device of claim 1 , wherein the first gate contact has a first height of between about 1 nm and about 1000 nm.
6 . The semiconductor device of claim 5 , wherein the first height is between about 1 nm and about 5 nm.
7 . The semiconductor device of claim 1 , wherein the maximum height of the encapsulant is between about 500 nm and about 1000 nm.
8 . A semiconductor device comprising:
a first bonding dielectric layer;
a first conductive bonding material embedded through the first bonding dielectric layer and in physical contact with a gate electrode contact, wherein the gate electrode contact has straight sidewalls from a top of the gate electrode contact to a bottom of the gate electrode contact;
a conductive material of a first semiconductor die bonded directly to the first conductive bonding material;
through vias extending through a semiconductor substrate of the first semiconductor die, wherein the through vias are all of the conductive vias extending through the semiconductor substrate, the through vias having a first height less than a second height of the first semiconductor die;
a second bonding dielectric layer bonded to the first bonding dielectric layer;
an encapsulant surrounding the first semiconductor die, the encapsulant having a first maximum height;
a second semiconductor die encapsulated within the encapsulant; and
second through vias extending through the encapsulant, the second through vias having the first maximum height.
9 . The semiconductor device of claim 8 , wherein the first conductive bonding material has a first dimension of between about 1 nm and about 7 nm.
10 . A semiconductor device comprising:
a first bonding dielectric layer adjacent to a first semiconductor substrate;
a first bonding conductor embedded within the first bonding dielectric layer and in physical contact with a first gate electrode contact;
a second bonding dielectric layer adjacent to a second semiconductor substrate different from the first semiconductor substrate, wherein the first semiconductor substrate has a first width extending from a first side of the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side of the first semiconductor substrate, wherein the second semiconductor substrate has a second width extending from a first side of the second semiconductor substrate to a second side of the second semiconductor substrate opposite the first side of the second semiconductor substrate, and wherein the first width is different than the second width;
through vias extending through the second semiconductor substrate to make physical contact with a second metallization layer in electrical contact with the second bonding dielectric layer, wherein the through vias are all of the conductive vias extending through the second semiconductor substrate;
a second bonding conductor embedded within the second bonding dielectric layer, the second bonding dielectric layer bonded to the first bonding dielectric layer;
a third semiconductor substrate encapsulated with the second semiconductor substrate by an encapsulant; and
at least one through encapsulant via extending through the encapsulant, the at least one through encapsulant via having a height at least as large as a largest height of the encapsulant.
11 . The semiconductor device of claim 10 , further comprising a third interconnection structure on an opposite side of the second semiconductor substrate from the first semiconductor substrate.
12 . The semiconductor device of claim 1 , a third interconnection structure adjacent to the third semiconductor substrate, wherein the third interconnection structure is bonded to the first bonding layer.
13 . The semiconductor device of claim 8 , wherein the first maximum height of the encapsulant is about 500 nm and about 1000 nm.
14 . The semiconductor device of claim 10 , wherein the largest height of the encapsulant has a height of between about 500 nm and about 1000 nm.
15 . The semiconductor device of claim 10 , wherein the first semiconductor substrate is part of an unfinished wafer.
16 . The semiconductor device of claim 10 , wherein the first gate electrode contact has a first width of between about 1 nm and about 180 nm.
17 . The semiconductor device of claim 8 , wherein the gate electrode contact has a first width of between about 1 nm and about 180 nm.
18 . The semiconductor device of claim 8 , wherein the gate electrode contact has a first width of between about 1 nm and about 5 nm.
19 . The semiconductor device of claim 8 , further comprising the second through vias extending through the third semiconductor substrate.
20 . The semiconductor device of claim 8 , further comprising an interconnection structure on an opposite side of the first semiconductor die from the first bonding dielectric layer.