Integrated packaging architecture with solder and non-solder interconnects
A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.
1 . A microelectronic assembly comprising:
a first integrated circuit (IC) die;
a second IC die; and
a third IC die,
wherein:
the first IC die is coupled to the second IC die with first interconnects having a first pitch,
the second IC die is coupled to the third IC die with second interconnects having a second pitch,
the first pitch is greater than the second pitch, and
the second pitch is less than 10 micrometers.
2 . The microelectronic assembly of claim 1 , wherein the first pitch is between 20 micrometers and 80 micrometers.
3 . The microelectronic assembly of claim 1 , wherein the first pitch is between 80 micrometers and 150 micrometers.
4 . The microelectronic assembly of claim 1 , wherein the second pitch is less than 1 micrometer.
5 . The microelectronic assembly of claim 1 , wherein:
the first IC die and the second IC die are attached to a surface of a first layer that includes IC dies,
the first IC die and the second IC die are in a second layer, and
the microelectronic assembly further comprises a third layer of IC dies over the second layer.
6 . The microelectronic assembly of claim 5 , wherein at least one IC die in the second layer is coupled to the third layer with interconnects of the second pitch.
7 . The microelectronic assembly of claim 1 , wherein:
the first interconnects comprise solder, and
the microelectronic assembly further comprises underfill around the first interconnects.
8 . An IC package comprising:
a first plurality of IC dies in a first layer;
a first IC die in a second layer, the first IC die coupled to a surface of the first layer with first interconnects having a first pitch; and
a second IC die in the second layer, the second IC die coupled to the surface of the first layer with second interconnects having a second pitch,
wherein:
the second pitch is greater than the first pitch, and
the first pitch is less than 10 micrometers.
9 . The IC package of claim 8 , wherein the first interconnects are hybrid bonds.
10 . The IC package of claim 8 , wherein:
the second interconnects are micro-bumps with solder caps,
a cross-sectional dimension of any one of the micro-bumps is between 10 micrometers and 40 micrometers, and
the second pitch is between 20 micrometers and 80 micrometers.
11 . The IC package of claim 8 , wherein:
the second interconnects are copper pillars and solder,
a cross-sectional dimension of any one of the copper pillars is between 40 micrometers and 75 micrometers, and
the second pitch is between 80 micrometers and 150 micrometers.
12 . The IC package of claim 8 , wherein the first IC die is a dummy IC die having no electrical functionalities.
13 . The IC package of claim 8 , wherein the first IC die is a stack of IC dies coupled to each other with interconnects having the first pitch.
14 . The IC package of claim 8 , wherein the first layer is coupled to a package substrate.