Integrated circuit packages with hybrid bonded dies and methods of manufacturing the same
Methods, apparatus, systems, and articles of manufacture are disclosed includes an integrated circuit (IC) package including a first die including a first surface and a second surface opposite the first surface, the first surface defined by a bulk semiconductor region of the first die, a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a bulk semiconductor region of the second die, the fourth surface facing towards the second surface, a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias disposed therein, and a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias disposed therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.
1 . An integrated circuit (IC) package comprising:
a first die including a first surface and a second surface opposite the first surface, the first surface defined by a first bulk semiconductor region of the first die;
a second die including a third surface and a fourth surface opposite the third surface, the third surface defined by a second bulk semiconductor region of the second die, the fourth surface facing towards the second surface;
a third die including a fifth surface and a sixth surface opposite the fifth surface, the fifth surface defined by a third bulk semiconductor region of the third die, the third die adjacent to the first die in a direction parallel to the fourth surface;
a first bonding layer between the second and fourth surfaces, the first bonding layer including first metal vias therein; and
a second bonding layer between the second and fourth surfaces, the second bonding layer including second metal vias therein, the first bonding layer in direct contact with the second bonding layer, ones of the first metal vias in direct contact with ones of the second metal vias to electrically couple the first die to the second die.
2 . The IC package of claim 1 , including a silicon lid adjacent the first surface of the first die.
3 . The IC package of claim 1 , wherein the first die includes a testing pad region, the testing pad region adjacent to the first bonding layer.
4 . The IC package of claim 1 , including a dielectric fill between the first die and the third die.
5 . The IC package of claim 4 , wherein the dielectric fill includes a bread-loafing line, the bread-loafing line closer to a lateral side of the first die adjacent the second surface than the bread-loafing line is to the lateral side of the first die adjacent the first surface.
6 . The IC package of claim 4 , including an adhesion layer between the dielectric fill and the first die and between the dielectric fill and the third die, the dielectric fill and the adhesion layer ending at the first bonding layer.
7 . The IC package of claim 1 , wherein at least one of the first metal vias is electrically isolated from metal interconnects within the first die.
8 . The IC package of claim 7 , wherein the first die includes first transistors and the second die includes second transistors, the first transistors are distal from the second transistors, the metal interconnects within the first die are adjacent to metal interconnects within the second die.
9 . The IC package of claim 1 , wherein the first bulk semiconductor region of the first die is distal from the second bulk semiconductor region of the second die.
10 . The IC package of claim 1 , including a via layer in-between the first bonding layer and the second surface of the first die.
11 . The IC package of claim 1 , wherein there is not a via layer between the first bonding layer and the second surface of the first die.
12 . The IC package of claim 1 , including a fusion bonding dielectric layer, the fusion bonding dielectric layer to align the first dies to a first carrier wafer, a first plurality of the first dies includes a first misalignment and a second plurality of the first dies includes a second misalignment, the first misalignment different than the second misalignment.
13 . A method of manufacturing the IC package of claim 1 , the method comprising:
positioning the first die onto a first carrier wafer with metal contacts of the first die adjacent to the first carrier wafer;
attaching a lid to the first die, the first die between the first carrier wafer and the lid;
removing the first carrier wafer from the first die to expose surfaces of the first die, the exposed surfaces of the first dies to include exposed portions of the metal contacts;
depositing the first bonding layer over the exposed surfaces of the first die;
adding the first metal vias into the first bonding layer, ones of the first metal vias to electrically contact ones of the exposed portions of the metal contacts;
providing the second die on a second wafer, the second die covered by the second bonding layer with the second metal vias extending through the second bonding layer;
attaching, via fusion bonding, the first metal vias to the second metal vias; and
attaching, via fusion bonding, the first bonding layer to the second bonding layer.
14 . The method of claim 13 , wherein the second wafer is a reconstituted carrier wafer.
15 . The method of claim 13 , including removing the second wafer from the second die.
16 . The method of claim 13 , wherein the second wafer is a non-reconstituted carrier wafer.
17 . The method of claim 13 , including depositing a dielectric fill.
18 . The method of claim 13 , wherein the lid includes silicon.
19 . The method of claim 13 , including fabricating a plurality of dies on a semiconductor wafer, the semiconductor wafer distinct and separate from the first carrier wafer, the plurality of dies including the first die.