Diode and bipolar junction transistor for 3D SFET with BSPDN structure
A (3D) stacked field effect transistors (SFETs) device includes a first transistor structure including a first source/drain (S/D) region and a second S/D region, the second S/D region including a first side and a second side facing opposite to the first side, and a second transistor structure including a third S/D region and a fourth S/D region, the fourth S/D region including a first side and a second side facing opposite to the first side. The first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region.
1 . A three-dimensional (3D) stacked field effect transistor (SFET) device, comprising:
a first transistor structure comprising a first source/drain (S/D) region and a second S/D region, the second S/D region comprising a first side and a second side facing opposite to the first side; and
a second transistor structure comprising a third S/D region and a fourth S/D region, the fourth S/D region comprising a first side and a second side facing opposite to the first side,
wherein the first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is directly merged with the first side of the fourth S/D region.
2 . The 3D SFET device of claim 1 , wherein the fourth S/D region comprises a collector electrode.
3 . The 3D SFET device of claim 1 , wherein the second S/D region comprises a base region and an emitter electrode.
4 . The 3D SFET device of claim 3 , wherein a first surface of the base region is substantially coplanar with a first surface of the emitter electrode,
wherein the first surface of the base region and the first surface of an electrode face of the emitter electrode opposite to a surface of the second side of the second S/D region.
5 . The 3D SFET device of claim 1 , further comprising an emitter electrode positioned in a channel of the first transistor structure and outside of the second S/D region.
6 . The 3D SFET device of claim 5 , wherein the second S/D region comprises a base region,
wherein a first surface of the base region is substantially coplanar with a first surface of the emitter electrode, and
wherein the first surface of the base region and the first surface of an electrode face of the emitter electrode opposite to a surface of the second side of the second S/D region.
7 . The 3D SFET device of claim 1 , wherein the first side of the fourth S/D region comprises:
an overlapping section that is merged with the second side of the second S/D region, and
a non-overlapping section.
8 . The 3D SFET device of claim 7 , wherein the 3D SFET device is connected to a backside power distribution network (BSPDN) by a contact provided on the non-overlapping section of the fourth S/D region.
9 . The 3D SFET device of claim 7 , wherein the non-overlapping section extends in a longitudinal direction with respect to the third S/D region.
10 . The 3D SFET device of claim 7 , further comprising a metal shim formed on the non-overlapping section of the fourth S/D region.
11 . The 3D SFET device of claim 10 , further comprising a contact provided on the metal shim.
12 . The 3D SFET device of claim 1 , wherein the second S/D region is larger than the fourth S/D region.
13 . The 3D SFET device of claim 1 , further comprising:
a first contact provided on the first side of the second S/D region;
a second contact provided on the first side of the second S/D region; and
a third contact provided on a second side of the fourth S/D region.
14 . The 3D SFET device of claim 13 , wherein the 3D SFET device is connected to a backside power distribution network (BSPDN) by at least one of the first contact, the second contact, and the third contact.
15 . The 3D SFET device of claim 1 , wherein
the first S/D region is connected to the second S/D in a first direction,
the third S/D region is connected to the fourth S/D region in the first direction, and
the second side of the second S/D region is merged with the first side of the fourth S/D region in a second direction different from the first direction.
16 . A three-dimensional (3D) stacked field effect transistor (SFET) device, comprising:
a first transistor structure comprising a first source/drain (S/D) region and a second S/D region, wherein the second S/D region comprises:
a first side,
a second side facing opposite to the first side,
a base region, and
an emitter electrode; and
a second transistor structure comprising a third S/D region and a fourth S/D region, the fourth S/D region comprising a first side and a second side facing opposite to the first side,
wherein the first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region,
wherein a first surface of the base region is substantially coplanar with a first surface of the emitter electrode, and
wherein the first surface of the base region and the first surface of an electrode face of the emitter electrode opposite to a surface of the second side of the second S/D region.
17 . The 3D SFET device of claim 16 , wherein the first side of the fourth S/D region comprises:
an overlapping section that is merged with the second side of the second S/D region, and
a non-overlapping section.
18 . The 3D SFET device of claim 17 , further comprising a contact provided on the non-overlapping section.
19 . The 3D SFET device of claim 16 , further comprising:
a first contact provided on the first side of the second S/D region;
a second contact provided on the first side of the second S/D region; and
a third contact provided on the second side of the fourth S/D region.
20 . A three-dimensional (3D) stacked field effect transistor (SFET) device, comprising:
a first transistor structure comprising a first source/drain (S/D) region and a second S/D region, wherein the second S/D region comprises:
a first side,
a second side facing opposite to the first side,
a base region, and
an emitter electrode; and
a second transistor structure comprising a third S/D region and a fourth S/D region, wherein the fourth S/D region comprises:
a first side,
a second side facing opposite to the first side, and
a collector electrode,
wherein the first transistor structure and the second transistor structure are merged such that the second side of the second S/D region is merged with the first side of the fourth S/D region,
wherein the fourth S/D region further comprises:
an overlapping section that is merged with the second side of the second S/D region;
a non-overlapping section; and
a metal shim provided on the non-overlapping section.
21 . The 3D SFET device of claim 20 , further comprising:
a first contact provided on a first surface of the base region;
a second contact provided on the first surface of the base region; and
a third contact provided on a first surface of the metal shim.