Clustering fine pitch micro-bumps for packaging and test

1 . An apparatus comprising:

a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface, wherein the array of micro-bumps comprises a pattern of a plurality of subarrays of micro-bumps, wherein each subarray includes a cluster of power micro-bumps, a cluster of ground micro-bumps, or a cluster of signal micro-bumps, wherein the micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the pattern are spaced apart by a card pitch that is an integer multiple of the chip pitch; and

a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface, wherein the card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps.

2 . The apparatus of claim 1 , further comprising an interposer that is disposed between the chip package and the laminate circuit card, wherein the interposer comprises:

a first surface that is adjacent to the chip connection surface;

an interconnect layer that is adjacent to the first surface and electrically connected to the micro-bumps;

a second surface that is opposite the first surface and adjacent to the laminate circuit card; and

an array of vias that extend from the interconnect layer to the second surface and are arranged in a plurality of subarrays, wherein each subarray of vias is electrically connected by the interconnect layer to a corresponding subarray of micro-bumps and is electrically connected at the second surface to a corresponding card pad.

3 . The apparatus of claim 2 , wherein the interconnect layer is arranged to evenly distribute electrical current from each subarray of micro-bumps to the corresponding subarray of vias.

4 . The apparatus of claim 2 , wherein each subarray of vias is arranged to evenly distribute electrical current from the interconnect layer to the corresponding card pad.

5 . The apparatus of claim 2 , further comprising a second chip package that has a second chip connection surface with a second array of micro-bumps that comprises a second plurality of subarrays of micro-bumps, wherein the interconnect layer of the interposer electrically connects selected micro-bumps on the chip package to corresponding micro-bumps on the second chip package.

6 . The apparatus of claim 1 , wherein the laminate circuit card comprises an interface layer at the card connection surface, wherein:

the interface layer comprises openings that are spaced at the chip pitch,

each opening corresponds to a micro-bump on the chip connection surface of the chip package, and

subarrays of the openings correspond to the card pads.

7 . The apparatus of claim 6 , further comprising a second chip package that has a second chip connection surface with a second array of micro-bumps that comprises a second plurality of subarrays of micro-bumps, wherein the interface layer comprises chip-to-chip connection traces that electrically connect selected micro-bumps on the chip package to corresponding micro-bumps on the second chip package.

8 . The apparatus of claim 1 , wherein the micro-bumps are arranged in orthogonal subarrays forming the pattern.

9 . The apparatus of claim 8 , wherein the chip package has a data signal pathway, there are nine positions in each subarray, and at least a central position in a subarray has a micro-bump that is connected to the data signal pathway of the chip package.

10 . The apparatus of claim 1 , wherein the card pads are arranged in an orthogonal array aligned to the pattern.

11 . The apparatus of claim 1 , wherein the micro-bumps are arranged in hexagonal subarrays forming the pattern.

12 . The apparatus of claim 11 , wherein the chip package has a data signal pathway, and wherein there are seven positions in each subarray and at least a central position in a subarray has a micro-bump that is connected to the data signal pathway of the chip package.

13 . The apparatus of claim 1 , wherein the card pads are arranged in a hexagonal array aligned to the pattern.

14 . The apparatus of claim 1 , wherein the plurality of subarrays of micro-bumps include a subarray including the cluster of power micro-bumps connected to a chip package power bus of the chip package, a subarray including the cluster ground micro-bumps connected to a chip ground bus of the chip package, and a subarray including the cluster of signal micro-bumps connected to a chip package data signal I/O of the chip package.

15 . An apparatus that comprises:

a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface, wherein the array of micro-bumps comprises a plurality of subarrays of micro-bumps, wherein the micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch; and

an interposer that is disposed adjacent to the chip connection surface of the chip package, wherein the interposer comprises:

a first surface that is adjacent to the chip connection surface;

an interconnect layer that is adjacent to the first surface and electrically connected to the micro-bumps;

a second surface that is opposite the first surface; and

an array of vias that extend from the interconnect layer to the second surface and are arranged in a plurality of subarrays, wherein each subarray of vias is electrically connected by the interconnect layer to a corresponding subarray of micro-bumps,

wherein each subarray of vias has fewer vias than a corresponding number of micro-bumps in the corresponding subarray of micro-bumps, and

the interconnect layer is arranged to evenly distribute electrical current from each subarray of micro-bumps to the corresponding subarray of vias.

16 . The apparatus of claim 15 , wherein each subarray of vias has approximately the same total cross-sectional area as the corresponding subarray of micro-bumps.

17 . The apparatus of claim 15 , wherein the micro-bumps of each subarray are one of power micro-bumps, ground micro-bumps, or signal micro-bumps.

18 . The apparatus of claim 15 , further comprising a laminate circuit card that has a card connection surface that faces the second surface of the interposer and that has an array of card pads on the card connection surface, wherein the card pads are spaced apart by the card pitch and arranged in a pattern,

wherein the subarrays of vias of the interposer are straight through electrical connections between the interconnect layer of the interposer and the subarrays of micro-bumps of the chip package.

19 . An apparatus comprising:

a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface, wherein the array of micro-bumps comprises a pattern of a plurality of subarrays of micro-bumps, wherein each subarray includes a cluster of power micro-bumps, a cluster of ground micro-bumps, or a cluster of signal micro-bumps, and the array of micro-bumps includes a subarray connected to a chip package power bus, a subarray connected to a chip ground bus, and a subarray connected to a chip package data signal I/O, wherein the micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the pattern are spaced apart by a card pitch that is an integer multiple of the chip pitch;

a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface, wherein the card pads are spaced apart by the card pitch; and

means for electrically connecting each of the card pads to a corresponding subarray of micro-bumps.

20 . The apparatus of claim 19 , wherein each of the card pads is aligned to the pattern and electrically connected with all of the micro-bumps of the corresponding subarray of micro-bumps.

21 . The apparatus of claim 19 , wherein the array of card pads includes at least one power card pad, at least one ground card pad, and a plurality of signal card pads.

22 . An apparatus that comprises:

a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface, wherein the array of micro-bumps comprises a plurality of subarrays of micro-bumps, wherein the micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch; and

an interposer that is disposed adjacent to the chip connection surface of the chip package, wherein the interposer comprises:

a first surface that is adjacent to the chip connection surface;

an interconnect layer that is adjacent to the first surface and electrically connected to the micro-bumps;

a second surface that is opposite the first surface; and

an array of vias that extend from the interconnect layer to the second surface and are arranged in a plurality of subarrays, wherein each subarray of vias is electrically connected by the interconnect layer to a corresponding subarray of micro-bumps,

wherein each subarray of vias has approximately the same total cross-sectional area as the corresponding subarray of micro-bumps.