Device including a chipset and an anti-vulcanization film

Inventors: Mingjun Zhu (Foshan, CN); Junzheng Li (Foshan, CN); Yan Chen (Foshan, CN); Meiqin Lei (Foshan, CN); Gaohui Wang (Foshan, CN); Zishan Lu (Foshan, CN); Danwei Li (Foshan, CN)

Assignee: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD.

H10W90/00 H10H20/01 H10H20/852

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Quick Facts

Patent No.: US 12667013
App. No.: 18/090,625
Granted: Jun 23, 2026
Kind: B2

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Abstract

Provided are a method for machining a device and the device. The method for machining a device includes die bonding, primary dicing, filling by a baffle wall material, grinding and secondary dicing. In the step of grinding machining, a semi-finished product is placed on a platform surface of a grinding and fixing platform, a grinding working end of a grinding device is controlled to operate, and with the platform surface of the grinding and fixing platform as a height reference, the grinding working end grinds from above the semi-finished product toward the grinding and fixing platform and operates to a preset height. Through the special machining process, the probability of the appearance of white glue on a top surface of the device is reduced, which is conducive to ensuring a production yield of the device.

Claims (36)

1 . A device, comprising a sub-circuit board, a chipset, a sub-encapsulation layer, a sub-baffle wall and a sub-top anti-vulcanization film;

wherein the chipset comprises a plurality of chips, wherein the plurality of chips are separately bonded on the sub-circuit board and encapsulated based on the sub-encapsulation layer;

a bottom surface contour of the sub-encapsulation layer is located in a region surrounded by an edge contour of the sub-circuit board;

the sub-baffle wall covers an outer side surface of the sub-encapsulation layer, extends from a bottom of the outer side surface of the sub-encapsulation layer toward an edge of the sub-circuit board and covers a top surface of the sub-circuit board; and

the sub-top anti-vulcanization film covers a top surface of the sub-encapsulation layer and a top surface of the sub-baffle wall;

wherein the sub-circuit board comprises a substrate, and the plurality of chips comprises a green light chip, a red light chip, and an infrared light chip;

wherein the device further comprises: a first front-side pad, a second front-side pad, a third front-side pad, a fourth front-side pad, a fifth front-side pad and a sixth front-side pad which are disposed on the substrate: a first chip slot and a second chip slot are disposed on the fourth front-side pad, and a third chip slot is disposed on the second front-side pad; and the red light chip is bonded on the first chip slot, the infrared light chip is bonded on the second chip slot, and the green light chip is bonded on the third chip slot;

wherein the device further comprises: a first back-side pad, a second back-side pad, a third back-side pad, a fourth back-side pad, a fifth back-side pad and a sixth back-side pad which are disposed on a back of the substrate, wherein the first back-side pad, the second back-side pad, the third back-side pad, the fourth back-side pad, the fifth back-side pad and the sixth back-side pad correspond to the first front-side pad, the second front-side pad, the third front-side pad, the fourth front-side pad, the fifth front-side pad and the sixth front-side pad respectively; and

wherein the back of the substrate is coated with green ink.

2 . The device according to claim 1 , further comprising a sub-side anti-vulcanization film, wherein the sub-side anti-vulcanization film covers the outer side surface of the sub-encapsulation layer, extends from the bottom of the outer side surface of the sub-encapsulation layer toward the edge of the sub-circuit board and covers the top surface of the sub-circuit board, and an outer side surface of the sub-side anti-vulcanization film is surrounded by the sub-baffle wall; and wherein the sub-top anti-vulcanization film further covers a top surface of the sub-side anti-vulcanization film.

3 . The device according to claim 1 , wherein the green light chip, the red light chip, and the infrared light chip are arranged on the substrate in delta arrangement.

4 . The device according to claim 1 , wherein a groove portion is disposed between the first chip slot and the second chip slot.

5 . The device according to claim 1 , wherein the red light chip and the infrared light chip are each a chip having a vertical structure.

6 . The device according to claim 1 , wherein the red light chip is connected to the fifth front-side pad through a first metal wire, the infrared light chip is connected to the first front-side pad through a second metal wire, and the green light chip is connected to the third front-side pad through a third metal wire.

7 . The device according to claim 1 , wherein a dimension of the green light chip is greater than a dimension of the red light chip or a dimension of the infrared light chip.

8 . The device according to claim 1 , wherein a height of a chip of the green light chip, the red light chip, and the infrared light chip is h, a height of the sub-encapsulation layer is H, and a constraint relationship between H and h is 1.5 h<H<4 h, where a value of H is in a range of 200 μm<H<600 μm.

9 . The device according to claim 1 , wherein the first back-side pad, the second back-side pad, the third back-side pad, the fourth back-side pad, the fifth back-side pad and the sixth back-side pad are disposed in two columns on both sides of the back of the substrate, and the third back-side pad and the fourth back-side pad are disposed at diagonal positions.

10 . The device according to claim 9 , wherein the third back-side pad is connected to the fourth back-side pad through a conductive line.

11 . The device according to claim 10 , wherein a position close to a middle of the back of the substrate is left blank to form an electrical identifier, and the electrical identifier is used for identifying polarities of the first back-side pad, the second back-side pad, the third back-side pad, the fourth back-side pad, the fifth back-side pad and the sixth back-side pad.

12 . The device according to claim 11 , wherein the conductive line is divided into three sections, and the three sections are connected based on a first right-angle turning portion and a second right-angle turning portion, and an intermediate section of the three sections is close to one column of the two columns of the first back-side pad, the second back-side pad, the third back-side pad, the fourth back-side pad, the fifth back-side pad and the sixth back-side pad.

13 . The device according to claim 10 , wherein a thickness of the conductive line is less than a thickness of any one of the first back-side pad, the second back-side pad, the third back-side pad, the fourth back-side pad, the fifth back-side pad and the sixth back-side pad.

14 . The device according to claim 1 , further comprising: a first metal guide column which is disposed on the first back-side pad and used for connecting to the first front-side pad, a second metal guide column which is disposed on the second back-side pad and used for connecting to the second front-side pad, a third metal guide column which is disposed on the third back-side pad and used for connecting to the third front-side pad, a fourth metal guide column which is disposed on the fourth back-side pad and used for connecting to the fourth front-side pad, a fifth metal guide column which is disposed on the fifth back-side pad and used for connecting to the fifth front-side pad, and a sixth metal guide column which is disposed on the sixth back-side pad and used for connecting to the sixth front-side pad.

15 . A device, comprising a sub-circuit board, a chipset, a sub-encapsulation layer, a sub-baffle wall and a sub-top anti-vulcanization film;

wherein the chipset comprises a plurality of chips, wherein the plurality of chips are separately bonded on the sub-circuit board and encapsulated based on the sub-encapsulation layer;

a bottom surface contour of the sub-encapsulation layer is located in a region surrounded by an edge contour of the sub-circuit board;

the sub-top anti-vulcanization film covers a top surface of the sub-encapsulation layer and a top surface of the sub-baffle wall;

wherein the sub-circuit board comprises a substrate, and the plurality of chips comprises a green light chip, a red light chip, and an infrared light chip;

wherein the back of the substrate is coated with ink; and

wherein a groove portion is disposed between the first chip slot and the second chip slot.

16 . The device according to claim 15 , further comprising a sub-side anti-vulcanization film, wherein the sub-side anti-vulcanization film covers the outer side surface of the sub-encapsulation layer, extends from the bottom of the outer side surface of the sub-encapsulation layer toward the edge of the sub-circuit board and covers the top surface of the sub-circuit board, and an outer side surface of the sub-side anti-vulcanization film is surrounded by the sub-baffle wall; and wherein the sub-top anti-vulcanization film further covers a top surface of the sub-side anti-vulcanization film.

17 . The device according to claim 15 , wherein the green light chip, the red light chip, and the infrared light chip are arranged on the substrate in delta arrangement.

18 . The device according to claim 15 , wherein the red light chip and the infrared light chip are each a chip having a vertical structure.

19 . The device according to claim 15 , wherein the red light chip is connected to the fifth front-side pad through a first metal wire, the infrared light chip is connected to the first front-side pad through a second metal wire, and the green light chip is connected to the third front-side pad through a third metal wire.