IP Library Granted Patent US 12667014
Granted Patent B2
US 12667014 · App. 18/169,175 · Granted Jun 23, 2026

Package structure and packaging method

Inventor: Xiaoxuan Chen (Hefei City, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10W90/00H10W72/01904H10W72/01951H10W72/926H10W72/932H10W72/942H10W72/944H10W72/9445H10W72/952H10W72/965H10W72/967H10W80/331H10W90/297H10W90/792
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Quick Facts
Patent No.
US 12667014
App. No.
18/169,175
Granted
Jun 23, 2026
Kind
B2
Abstract

A package structure includes at least two semiconductor structures that are stacked onto one another. The first surface of one semiconductor structure of the at least two semiconductor structures that are stacked onto one another directly faces toward the second surface of another semiconductor structure of the at least two semiconductor structures which is adjacent to said one semiconductor structure; the first metal layer of said one semiconductor structure is in contact with and bonded to the third metal layer of said another semiconductor structure; and the second metal layer of said one semiconductor structure is in contact with and bonded to the fourth metal layer of said another semiconductor structure.

Claims (18)

1 . A package structure, comprising:

at least two semiconductor structures that are stacked onto one another, each of the at least two semiconductor structures comprising a first surface and a second surface that are opposite to each other, each of the at least two semiconductor structures comprising a circuit area and a support area, and at least one conductive structure being disposed in the circuit area in each of the at least two semiconductor structures; each of the at least two semiconductor structures further comprising:

at least one first metal layer and a second metal layer, the at least one first metal layer being located on the first surface in the circuit area, and the second metal layer being located on the first surface in the support area;

at least one third metal layer and a fourth metal layer, the at least one third metal layer being located on the second surface in the circuit area and being electrically connected to the at least one conductive structure, and the fourth metal layer being located on the second surface in the support area,

wherein the first surface of one semiconductor structure of the at least two semiconductor structures that are stacked onto one another directly faces toward the second surface of another semiconductor structure of the at least two semiconductor structures which is adjacent to said one semiconductor structure; the at least one first metal layer of said one semiconductor structure is contact with and bonded to the at least one third metal layer of said another semiconductor structure adjacent to said one semiconductor structure; and the second metal layer of said one semiconductor structure is in contact with and bonded to the fourth metal layer of said another semiconductor structure adjacent to said one semiconductor structure; and

the at least one conductive structure protrudes from the second surface in the circuit area; each of the at least two semiconductor structures further comprises an insulating layer; the insulating layer is located on the second surface in the circuit area; the insulating layer is located on side surfaces of the at least one conductive structure; and the at least one third metal layer is located on a surface of the insulating layer.

2 . The package structure of claim 1 , wherein the second metal layer located in the support area is an entire continuous film layer; and the fourth metal layer located in the support area is an entire continuous film layer.

3 . The package structure of claim 1 , wherein each of the at least two semiconductor structure comprises a plurality of first metal layers spaced apart from each other; and in an arrangement direction of the support area and the circuit area, a ratio of a spacing between any adjacent first metal layers of the plurality of first metal layers to a width of each of the plurality of first metal layers ranges from 1/12 to ¾.

4 . The package structure of claim 3 , wherein in the arrangement direction of the support area and the circuit area, the width of each of the plurality of first metal layers ranges from 40 μm to 60 μm.

5 . The package structure of claim 3 , wherein in the arrangement direction of the support area and the circuit area, the spacing between the any adjacent first metal layers of the plurality of first metal layers ranges from 5 μm to 30 μm.

6 . The package structure of claim 1 , wherein an orthographic projection of the at least one third metal layer on the first surface is located within an orthographic projection of the at least one first metal layer that is in contact with and bonded to the at least one third metal layer on the first surface.

7 . The package structure of claim 1 , wherein a material of the at least one first metal layer is the same as a material of the second metal layer.

8 . The package structure of claim 1 , wherein a material of the at least one first metal layer includes copper, aluminum, or tungsten.

9 . The package structure of claim 1 , wherein in a direction from the first surface to the second surface, a thickness of the at least one first metal layer is the same as a thickness of the at least one third metal layer.

10 . The package structure of claim 1 , wherein in a direction from the first surface to the second surface, a thickness of the at least one first metal layer ranges from 1 μm to 100 μm.

11 . The package structure of claim 1 , wherein the insulating layer comprises:

a first dielectric layer, the first dielectric layer being located on the second surface in the circuit area, and the first dielectric layer being located on a side surface of the at least one conductive structure; and

a second dielectric layer, the second dielectric layer being located between the first dielectric layer and the at least one third metal layer.