Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates
A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.
1 . A chiplet-based multi-chip module (MCM) to mount to a main substrate, comprising:
a package substrate without an interposer, the package substrate separate from the main substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first interface beachfront of a first longitudinal length, the first interface beachfront formed along a first edge of the first IC chiplet and comprising a first set of die-to-die (D2D) interface circuits; and
a first set of peripheral chiplets coupled to the package substrate in a first collinear fanout arrangement with respect to the first interface beachfront of the first IC chiplet, the first collinear fanout arrangement comprising a second longitudinal length that is longer than the first longitudinal length, the first set of peripheral chiplets coupled to the first set of D2D interfaces in a one-to-one relationship via a first set of long-reach links.
2 . The chiplet-based MCM of claim 1 , wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces.
3 . The chiplet-based MCM of claim 1 , wherein:
the first IC chiplet comprises a processing IC chiplet.
4 . The chiplet-based MCM of claim 1 , wherein:
the first set of peripheral chiplets comprises multiple photonic IC chiplets.
5 . The chiplet-based MCM of claim 1 , wherein:
the first set of peripheral chiplets comprises multiple memory chiplets.
6 . The chiplet-based MCM of claim 5 , wherein:
each of the multiple memory chiplets comprises
a base die; and
a memory stack disposed on the base die.
7 . The chiplet-based MCM of claim 6 , wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
8 . The chiplet-based MCM of claim 1 , wherein:
the first set of long-reach links are free to be different lengths.
9 . The chiplet-based MCM of claim 8 , wherein:
the first set of long-reach links are of staggered lengths.
10 . The chiplet-based MCM of claim 2 , wherein:
the first set of D2D interfaces comprises a first set of Universal Chiplet Interconnect Express (UCIe) D2D interfaces.
11 . The chiplet-based MCM of claim 1 , wherein:
the first integrated circuit (IC) chiplet comprises a second interface beachfront of a third longitudinal length, the second interface beachfront formed along a second edge of the first IC chiplet and comprising a second set of die-to-die (D2D) interface circuits; and
wherein the chiplet-based MCM further comprises a second set of peripheral chiplets coupled to the package substrate in a second collinear fanout arrangement with respect to the second interface beachfront of the first IC chiplet, the second collinear fanout arrangement comprising a fourth longitudinal length that is longer than the third longitudinal length, the second set of peripheral chiplets coupled to the second set of D2D interfaces in a one-to-one relationship via a second set of long-reach links.
12 . A chiplet-based multi-chip module (MCM) to mount to a main substrate, comprising:
a package substrate without an interposer, the package substrate separate from the main substrate;
a first integrated circuit (IC) chiplet coupled to the package substrate and comprising a first set of die-to-die (D2D) interface circuits disposed proximate a first edge of the first IC chiplet and a second set of D2D interface circuits disposed proximate a second edge of the first IC chiplet;
a first set of peripheral chiplets coupled to the first set of D2D interface circuits via a first set of links, the first set of links routed along a first set of traces of the package substrate;
a second set of peripheral chiplets coupled to the second set of D2D interface circuits via a second set of links, the second set of links routed along a second set of traces of the package substrate; and
wherein adjacent peripheral chiplets of the first set of peripheral chiplets are positioned in a first collinear fanout arrangement with respect to the first IC chiplet, and wherein adjacent peripheral chiplets of the second set of peripheral chiplets are positioned in a second collinear fanout arrangement with respect to the first IC chiplet.
13 . The chiplet-based MCM of claim 12 , wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a first parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces; and
the second collinear fanout arrangement of the second set of peripheral chiplets defines a second parallel spaced-apart relationship of the second set of peripheral chiplets with respect to the second set of D2D interfaces.
14 . The chiplet-based MCM of claim 12 , wherein:
the first IC chiplet comprises a processing IC chiplet.
15 . The chiplet-based MCM of claim 12 , wherein:
the first set of peripheral chiplets comprises multiple photonic IC chiplets.
16 . The chiplet-based MCM of claim 12 , wherein:
the first set of peripheral chiplets comprises multiple memory chiplets.
17 . The chiplet-based MCM of claim 16 , wherein:
each of the multiple memory chiplets comprises
a base die; and
a memory stack disposed on the base die.
18 . The chiplet-based MCM of claim 17 , wherein:
the memory stack comprises a high-bandwidth memory (HBM) stack of dynamic random access memory (DRAM).
19 . The chiplet-based MCM of claim 12 , wherein:
the first set of links and the second set of links are free to be different lengths.
20 . The chiplet-based MCM of claim 19 , wherein:
the first set of links and the second set of links are of staggered lengths.
21 . The chiplet-based MCM of claim 12 , wherein:
the first set of D2D interfaces and the second set of D2D interfaces comprise respective first and second sets of Universal Chiplet Interconnect Express (UCIe) D2D interfaces.
22 . A method of operation in a chiplet-based multi-chip module (MCM), comprising:
interfacing, on a package substrate without an interposer, a first set of D2D interfaces of a first integrated circuit (IC) chiplet to a first set of peripheral chiplets via a first set of long-reach links, the interfacing of the first IC chiplet to the first set of peripheral chiplets comprising positioning adjacent peripheral chiplets of the first set of peripheral chiplets in a first collinear fanout arrangement with respect to the first IC chiplet;
interfacing, on the package substrate, a second set of D2D interfaces of the first IC chiplet to a second set of peripheral chiplets via a second set of long-reach links, wherein the interfacing of the first IC chiplet to the second set of peripheral chiplets comprises positioning adjacent peripheral chiplets of the second set of peripheral chiplets in a second collinear fanout arrangement with respect to the first IC chiplet.
23 . The method of claim 22 , wherein:
the first collinear fanout arrangement of the first set of peripheral chiplets defines a first parallel spaced-apart relationship of the first set of peripheral chiplets with respect to the first set of D2D interfaces; and
the second collinear fanout arrangement of the second set of peripheral chiplets defines a second parallel spaced-apart relationship of the second set of peripheral chiplets with respect to the second set of D2D interfaces.