Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.
1 . A semiconductor memory device comprising:
a memory cell array above a substrate;
a first circuit on a portion of the substrate beneath the memory cell array; and
a pattern for photolithography provided on a central side of the substrate compared to the first circuit,
wherein the memory cell array includes a plurality of first conductive layers stacked in a first direction above the substrate, and a pillar penetrating through the first conductive layers in the first direction.
2 . The semiconductor memory device according to claim 1 , wherein
the pattern is an alignment mark.
3 . The semiconductor memory device according to claim 2 , wherein
the alignment mark includes first patterns, and second patterns arranged outside the first patterns with predetermined spaces therebetween.
4 . The semiconductor memory device according to claim 3 , wherein
the predetermined spaces are equal to one another.
5 . The semiconductor memory device according to claim 1 , wherein
the pattern is a dimension measurement mark.
6 . The semiconductor memory device according to claim 1 , wherein
the pattern includes first patterns, and second patterns arranged outside the first patterns with predetermined spaces therebetween.
7 . The semiconductor memory device according to claim 1 , wherein
the pattern includes first patterns arranged at portions corresponding to sides of a rectangle, and second patterns arranged outside the first patterns with predetermined spaces therebetween.
8 . The semiconductor memory device according to claim 1 , further comprising:
a first chip including the memory cell array; and
a second chip including the first circuit and the pattern.
9 . The semiconductor memory device according to claim 8 , wherein
the pattern is provided between the substrate and the memory cell array.
10 . The semiconductor memory device according to claim 1 , further comprising:
a first chip including the memory cell array, the first circuit and the pattern.
11 . The semiconductor memory device according to claim 1 , further comprising:
a plurality of memory cell arrays including the memory cell array; and
a plurality of row decoders on the substrate and connected to the plurality of memory cell arrays, wherein
the pattern is provided between the plurality of row decoders.
12 . The semiconductor memory device according to claim 1 , further comprising:
a plurality of memory cell arrays including the memory cell array; and
a plurality of sense amplifiers on the substrate and connected to the plurality of memory cell arrays, wherein
the pattern is provided between the plurality of sense amplifiers.
13 . A semiconductor memory device comprising:
a memory cell array; and
a pad region provided adjacent to the memory cell array, and including a plurality of first pads and a pattern for photolithography, wherein
the plurality of first pads are for connecting a memory controller provided outside of the semiconductor memory device, and
the pattern includes first patterns arranged at portions corresponding to sides of a rectangle, and second patterns arranged outside of the first patterns with predetermined spaces therebetween.