Semiconductor package

1 . A semiconductor package, comprising:

a first redistribution substrate;

a first semiconductor chip disposed on the first redistribution substrate;

a first mold layer that covers the first semiconductor chip and the first redistribution substrate;

a second redistribution substrate disposed on the first mold layer;

a second semiconductor chip disposed on the second redistribution substrate, wherein the second semiconductor chip includes

a second-chip first conductive bump and a second-chip second conductive bump that does not overlap the first semiconductor chip,

a first sidewall that overlaps the first semiconductor chip, and

a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other; and

a first mold via that penetrates the first mold layer,

wherein the second-chip first conductive bump and the second-chip second conductive bump are adjacent to each other, and

a center of the first mold via is disposed between the second-chip first conductive bump and the second-chip second conductive bump.

2 . The semiconductor package of claim 1 , wherein

the first redistribution substrate includes a first via structure connected to the first mold via,

the second redistribution substrate includes a second via structure on the first mold via,

the second via structure overlaps the second-chip first conductive bump and the second-chip second conductive bump, and

the second via structure, the first mold via, and the first via structure are vertically aligned with each other.

3 . The semiconductor package of claim 2 , wherein each of the first via structure and the second via structure includes a plurality of stacked vias.

4 . The semiconductor package of claim 2 , wherein

the second via structure connects to the second-chip first conductive bump and the second-chip second conductive bump.

5 . The semiconductor package of claim 1 , wherein

the first mold via connects the second-chip first conductive bump and the second-chip second conductive bump to the first redistribution substrate.

6 . The semiconductor package of claim 1 , wherein

the first semiconductor chip includes a first-chip first conductive bump and a first-chip second conductive bump that are spaced apart from each other, and

the first redistribution substrate includes:

a redistribution pattern that connects the first mold via to the first-chip first conductive bump; and

a via structure connected to the first-chip second conductive bump and spaced apart from the redistribution pattern, wherein the via structure overlaps the first-chip second conductive bump.

7 . The semiconductor package of claim 1 , further comprising:

a first redistribution pattern that is in contact with a bottom surface of the first mold via, and

a second redistribution pattern that is in contact with a top surface of the first mold via, wherein

each of the first redistribution pattern and the second redistribution pattern includes a via part and a line part connected to the second-chip first conductive bump, and

the via part of the first redistribution pattern and the via part of the second redistribution pattern overlap each other.

8 . The semiconductor package of claim 7 , wherein

the via part of the first redistribution pattern and the via part of the second redistribution pattern are vertically aligned each other.

9 . The semiconductor package of claim 7 , wherein

the via part of the first redistribution pattern is disposed on the line part of the first redistribution pattern,

the via part of the second redistribution pattern is disposed on the line part of the second redistribution pattern.

10 . The semiconductor package of claim 1 , further comprising:

a second mold via that penetrates the first mold layer and is spaced apart from the first mold via,

wherein the second semiconductor chip further includes a second-chip third conductive bump that overlaps the second mold via.

11 . The semiconductor package of claim 1 , wherein

a shortest distance between the center of the first mold via and the second-chip first conductive bump is a same as a shortest distance between the center of the first mold via and the second-chip second conductive bump.

12 . A semiconductor package, comprising:

a first redistribution substrate;

a first semiconductor chip disposed on the first redistribution substrate;

a first mold layer that covers the first semiconductor chip and the first redistribution substrate;

a second redistribution substrate disposed on the first mold layer;

a second semiconductor chip disposed on the second redistribution substrate, wherein a portion of the second semiconductor chip overlaps a portion of the first semiconductor chip; and

a first mold via at a side of the first semiconductor chip, wherein the first mold via penetrates the first mold layer and overlaps the second semiconductor chip;

wherein the second semiconductor chip includes:

a second-chip first conductive bump and a second-chip second conductive bump that does not overlap the first semiconductor chip and is connected to the first mold via; and

a second-chip third conductive bump that overlaps the first semiconductor chip,

wherein the second-chip first conductive bump and the second-chip second conductive bump are adjacent to each other,

a center of the first mold via is disposed between the second-chip first conductive bump and second-chip second conductive bump,

wherein the second semiconductor chip has a first width in a first direction,

wherein a portion of the second semiconductor chip has a second width in the first direction, and the portion of the second semiconductor chip overlaps the first semiconductor chip, and

wherein the second width is about 10% to about 90% of the first width.

13 . The semiconductor package of claim 12 , wherein

the first redistribution substrate includes a first via structure connected to the first mold via,

the second redistribution substrate includes a second via structure connected to the second-chip first conductive bump and the second-chip second conductive bump,

the second via structure overlaps the second-chip first conductive bump and the second-chip second conductive bump, and

the second via structure, the first mold via, and the first via structure are vertically aligned with each other.

14 . The semiconductor package of claim 13 , further comprising

a solder ball bonded to the first redistribution substrate and connected to the first via structure,

wherein the first redistribution substrate further includes an under-bump between the first via structure and the solder ball, and

the first via structure, the under-bump, and the solder ball are vertically aligned with each other.

15 . The semiconductor package of claim 12 , wherein

the first mold via connects the second-chip first conductive bump and the second-chip second conductive bump to the first redistribution substrate.

16 . A semiconductor package, comprising:

a first redistribution substrate;

a first semiconductor chip disposed on the first redistribution substrate;

a first mold layer that covers the first semiconductor chip and the first redistribution substrate;

a second redistribution substrate disposed on the first mold layer; and

a second semiconductor chip disposed on the second redistribution substrate,

wherein the second semiconductor chip includes

a second-chip first conductive bump that does not overlap the first semiconductor chip,

a third semiconductor chip disposed on the second redistribution substrate and spaced apart from the second semiconductor chip, and

a first mold via that penetrates the first mold layer,

wherein the second semiconductor chip includes a first sidewall and a second sidewall that are opposite to each other,

wherein the third semiconductor chip includes a first sidewall and a second sidewall that are opposite to each other,

wherein the first sidewall of the second semiconductor chip and the first sidewall of the third semiconductor chip overlap the first semiconductor chip, and

wherein the second sidewall of the second semiconductor chip and the second sidewall of the third semiconductor chip do not overlap the first semiconductor chip.

17 . The semiconductor package of claim 16 , wherein

the second semiconductor chip further includes a second-chip second conductive bump disposed on the second redistribution substrate and spaced apart from the second-chip first conductive bump,

a center of the first mold via is disposed between the second-chip first conductive bump and the second-chip second conductive bump.

18 . The semiconductor package of claim 16 , further comprising:

a second mold via that penetrates the first mold layer and is spaced apart from the first mold via,

wherein the third semiconductor chip includes a third-chip first conductive bump and a third-chip second conductive bump disposed on the second redistribution substrate and spaced apart from each other,

the third-chip first conductive bump does not overlap the first semiconductor chip, and

the third-chip second conductive bump overlaps the first semiconductor chip.

19 . The semiconductor package of claim 18 , wherein

the first redistribution substrate includes a via structure connected to the second mold via, and

the via structure, the second mold via and the third-chip first conductive bump are vertically aligned with each other.

20 . The semiconductor package of claim 16 , wherein

the second semiconductor chip further includes a second-chip third conductive bump disposed on the second redistribution substrate and spaced apart from the second-chip first conductive bump, and

the second-chip third conductive bump overlaps the first semiconductor chip.