Package comprising a substrate with post interconnects and a solder resist layer having a cavity

1 . A package comprising:

a first substrate comprising:

at least one first dielectric layer;

a first plurality of interconnects; and

a first solder resist layer;

a first integrated device coupled to the first substrate;

a second substrate comprising:

a first surface and a second surface;

at least one second dielectric layer;

a second plurality of interconnects, wherein the second plurality of interconnects comprises a plurality of post interconnects; and

a second solder resist layer coupled to the second surface of the second substrate,

wherein the second solder resist layer comprises:

a first solder resist layer portion comprising a first thickness, wherein the first solder resist layer portion vertically overlaps with the first integrated device; and

a second solder resist layer portion comprising a second thickness that is greater than the first thickness, wherein the second solder resist layer portion is coupled to and touching a side portion of each post interconnect from the plurality of post interconnects,

wherein the second surface of the second substrate faces in the direction of the first substrate,

wherein the second solder resist layer includes a cavity, and

wherein the cavity is located laterally to the second solder resist layer portion and a post interconnect from the plurality of post interconnects,

wherein the cavity is located vertically between the first integrated device and the second solder resist layer, and

wherein the second solder resist layer directly touches the at least one second dielectric layer of the second substrate,

a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate,

wherein the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate,

wherein the plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate, and

wherein a first solder interconnect from the plurality of solder interconnects directly touches (i) a ball interconnect from the plurality of ball interconnects, (ii) an interconnect from the first plurality of interconnects of the first substrate, (iii) the post interconnect from the plurality of post interconnects of the second substrate, (iv) a first solder resist layer of the first substrate and (v) the second solder resist layer of the second substrate, and

an encapsulation layer located between the first substrate and the second substrate,

wherein the encapsulation layer directly touches the first solder resist layer of the first substrate and the second solder resist layer of the second substrate, and

wherein the encapsulation layer is a different material from the first solder resist layer and the second solder resist layer.

2 . The package of claim 1 ,

wherein each post interconnect from the plurality of post interconnects is laterally surrounded by the second solder resist layer,

wherein an entire side portion of each post interconnect from the plurality of post interconnects is touched by the second solder resist layer,

wherein the post interconnect comprises a thickness and a width,

wherein the post interconnect directly touches another interconnect from the second plurality of interconnects of the second substrate, and

wherein the thickness of the post interconnect is greater than the width of the post interconnect.

3 . The package of claim 1 , wherein the plurality of ball interconnects include neighboring ball interconnects that have a pitch that is equal or less than 270 micrometers.

4 . The package of claim 3 , wherein the plurality of ball interconnects include neighboring ball interconnects that have a pitch that is in a range of about 200-270 micrometers.

5 . The package of claim 1 , wherein the plurality of balls interconnects include at least 300 ball interconnects that laterally surround the first integrated device.

6 . The package of claim 1 ,

wherein a portion of the encapsulation layer is located vertically between the second solder resist layer and the first integrated device,

wherein the encapsulation layer is located at least partially in the cavity,

wherein the portion of the encapsulation layer that is located vertically between the second solder resist layer and the first integrated device, is located laterally to the second solder resist layer portion and the post interconnect.

7 . The package of claim 6 , wherein the encapsulation layer at least partially encapsulates the first integrated device, the plurality of ball interconnects and the plurality of solder interconnects.

8 . The package of claim 1 , further comprising a second integrated device coupled to the first surface of the second substrate, wherein a vertical gap between the second solder resist layer of the second substrate and the back side of the first integrated device is less than another vertical gap between the second solder resist layer of the second substrate and the first solder resist layer of the first substrate.

9 . The package of claim 1 , wherein the plurality of ball interconnects include copper core balls (CCBs).

10 . A package comprising:

a first substrate comprising:

at least one first dielectric layer,

a first plurality of interconnects, wherein the first plurality of interconnects comprises a first plurality of post interconnects; and

a first solder resist layer;

a first integrated device coupled to the first substrate;

a second substrate comprising:

a first surface and a second surface;

at least one second dielectric layer;

a second plurality of interconnects, wherein the second plurality of interconnects comprises a second plurality of post interconnects; and

a second solder resist layer coupled to the second surface of the second substrate, wherein the second solder resist layer comprises:

a first solder resist layer portion comprising a first thickness, wherein the first solder resist layer portion vertically overlaps with the first integrated device; and

a second solder resist layer portion comprising a second thickness that is greater than the first thickness, wherein the second solder resist layer portion is coupled to and touching a side portion of each post interconnect from the second plurality of post interconnects,

wherein the second solder resist layer includes a cavity,

wherein the cavity is located laterally to the second solder resist layer portion and a post interconnect from the plurality of post interconnects, and

wherein the cavity is located vertically between the first integrated device and the second solder resist layer, and

wherein the second solder resist layer directly touches the at least one second dielectric layer of the second substrate,

means for inter-substrate interconnection coupled to the first substrate and the second substrate,

wherein the means for inter-substrate interconnection is located between the first substrate and the second substrate,

wherein the means for inter-substrate interconnection is configured to couple and directly touch the first plurality of post interconnects of the first substrate and the second plurality of post interconnects of the second substrate,

wherein the means for inter-substrate interconnection includes a plurality of ball interconnects and a plurality of solder interconnects, and

wherein a first solder interconnect from the plurality of solder interconnects directly touches (i) a first ball interconnect from the plurality of ball interconnects, (ii) a post interconnect from the first plurality of post interconnects of the first substrate, (iii) the post interconnect from the second plurality of post interconnects of the second substrate, (iv) a first solder resist layer of the first substrate and (v) the second solder resist layer of the second substrate.

11 . The package of claim 10 , wherein the first ball interconnect is the only ball interconnect located vertically between (i) the post interconnect from the first plurality of post interconnects of the first substrate and (ii) the post interconnect from the second plurality of post interconnects of the second substrate.

12 . The package of claim 10 ,

wherein an entire side portion of each post interconnect from the plurality of post interconnects is touched by the second solder resist layer,

wherein the post interconnect from the second plurality of post interconnects of the second substrate, comprises a thickness and a width,

wherein the post interconnect directly touches another interconnect from the second plurality of interconnects of the second substrate and

wherein the thickness of the post interconnect from the second plurality of post interconnects of the second substrate, is greater than the width of the post interconnect.

13 . The package of claim 10 , wherein the means for inter-substrate interconnection includes interconnects that have a pitch that is in a range of about 150-270 micrometers.

14 . The package of claim 10 , further comprising an encapsulation layer located at least partially in the cavity of the second solder resist layer,

wherein the encapsulation layer directly touches the first solder resist layer of the first substrate and the second solder resist layer of the second substrate, and

wherein the encapsulation layer is a different material from the first solder resist layer and the second solder resist layer.

15 . The package of claim 14 , wherein a portion of the encapsulation layer that is located vertically between the second solder resist layer and the first integrated device, is located laterally to the second solder resist layer portion and the post interconnect from the second plurality of post interconnects.

16 . The package of claim 15 , wherein the encapsulation layer is a single encapsulation layer that is the only encapsulation layer located between the first substrate and the second substrate.

17 . The package of claim 16 , wherein the encapsulation layer directly touches the second solder resist layer and the first integrated device.

18 . The package of claim 6 , wherein the encapsulation layer is a single encapsulation layer that directly touches the second solder resist layer and the first integrated device, wherein the single encapsulation layer is the only encapsulation layer located between the first substrate and the second substrate.