Integrated sensor and method of timing monitoring in an integrated sensor
The integrated sensor has a clock which provides a clock signal having a clock frequency; a digital detector which detects a power grid signal and generates a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and a timing monitoring stage which receives the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal. The timing monitoring stage also compares the reference digital signal with the nominal signal and, in response, provides an error signal indicative of a timing error between the reference digital signal and the nominal signal.
1 . An integrated sensor, comprising:
a clock configured to provide a clock signal having a clock frequency;
a digital detector configured to:
detect a power grid signal; and
generate a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and
a timing monitor configured to:
receive the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal in order to compare the reference digital signal with the nominal signal, the nominal signal being indicative of a nominal digital frequency of the reference digital signal, the nominal digital frequency being a function of a nominal data rate of the reference digital signal and of a grid frequency of the power grid signal; and
in response to the comparison, provide an error signal indicative of a timing error between the reference digital signal and the nominal signal,
the timing monitor including an estimator configured to determine, from the reference digital signal, a timing parameter indicative of an effective digital frequency of the reference digital signal, the effective digital frequency being a function of an effective data rate of the reference digital signal and of the grid frequency of the power grid signal, the timing error being indicative of a difference between the effective digital frequency and the nominal digital frequency.
2 . The integrated sensor according to claim 1 , wherein the digital detector includes:
a reference detector configured to wirelessly detect the power grid signal, and generate an analog signal indicative of the detected power grid signal; and
an analog-to-digital converter configured to receive and discretize the analog signal based on the clock signal.
3 . The integrated sensor according to claim 2 , wherein the reference detector includes an electrode sensitive to a variation of electrostatic charge caused by the power grid signal.
4 . The integrated sensor according to claim 1 , wherein
the timing parameter is indicative of a number of samples per period of the reference digital signal, and
the estimator includes:
a period detector configured to detect a period of the reference digital signal; and
a counter configured to determine the number of samples per period of the reference digital signal.
5 . The integrated sensor according to claim 4 , wherein the period detector is configured to detect a period of the reference digital signal by detecting one of zero crossings, peaks, or valleys of the reference digital signal.
6 . The integrated sensor according to claim 1 , wherein
the timing parameter is indicative of a peak frequency of a spectrum of the reference digital signal, and
the estimator is configured to perform a frequency analysis of the reference digital signal, and detect the peak frequency based on a result of the frequency analysis.
7 . The integrated sensor according to claim 1 , wherein
the timing monitor includes a phase-locked circuit including the clock,
the nominal signal is the clock signal, and
the phase-locked circuit is configured to use the reference digital signal as a locking signal for the clock signal.
8 . The integrated sensor according to claim 1 , wherein
the digital detector is a first digital detector,
the integrated sensor includes a second digital detector configured to:
detect a physical quantity; and
provide an output digital signal indicative of the detected physical quantity and having a sample rate which is a function of the clock frequency.
9 . The integrated sensor according to claim 8 , wherein the timing monitor includes a trimming module configured to:
receive the error signal; and
provide a trimming signal configured to compensate for the timing error.
10 . The integrated sensor according to claim 9 , wherein the second digital detector is configured to:
receive the trimming signal; and
in response to the trimming signal being received, modify the sample rate of the output digital signal.
11 . The integrated sensor according to claim 9 , wherein the clock is configured to:
receive the trimming signal; and
in response to the trimming signal being received, modify the clock frequency of the clock signal.
12 . A method, comprising:
generating, by a clock, a clock signal having a clock frequency;
detecting, by a digital detector, a power grid signal;
generating, by the digital detector, a reference digital signal indicative of the detected power grid signal and having a sample rate which is a function of the clock frequency;
comparing, by a timing monitor, the reference digital signal with a nominal signal indicative of a nominal timing of the reference digital signal, the nominal signal is indicative of a nominal digital frequency of the reference digital signal, the nominal digital frequency being a function of a nominal data rate of the reference digital signal and of a grid frequency of the power grid signal; and
providing, by the timing monitor, an error signal indicative of a timing error between the reference digital signal and the nominal signal, in response to the comparison between the reference digital signal and the nominal signal,
comparing the reference digital signal with the nominal signal includes determining, from the reference digital signal, a timing parameter indicative of an effective digital frequency of the reference digital signal, the effective digital frequency being a function of an effective data rate of the reference digital signal and of the grid frequency of the power grid signal, the timing error being indicative of a difference between the effective digital frequency and the nominal digital frequency.
13 . The method according to claim 12 , further comprising:
providing a trimming signal as a function of the error signal, the trimming signal being configured to compensate for the timing error.
14 . A device, comprising:
a clock configured to generate a clock signal having a clock frequency;
a reference detector configured to detect electrostatic charge variation of a power grid signal, and generate a reference digital signal based on the electrostatic charge variation and the clock signal; and
a rate monitor configured to:
receive a nominal value signal indicative of a nominal digital frequency of the reference digital signal;
determine an effective digital frequency of the reference digital signal;
determine a difference between the effective digital frequency and the nominal digital frequency; and
change the clock frequency based on the difference between the effective digital frequency and the nominal digital frequency.
15 . The device of claim 14 , wherein the reference digital signal has a sample rate that is a function of the clock frequency.
16 . The device of claim 14 , wherein the nominal digital frequency is a function of a nominal data rate of the reference digital signal and of a grid frequency of the power grid signal.
17 . The device of claim 14 , wherein the effective digital frequency is a function of an effective data rate of the reference digital signal and of a grid frequency of the power grid signal.
18 . The device of claim 14 , wherein
the rate monitor is configured to generate a trimming signal that is a function of the difference between the effective digital frequency and the nominal digital frequency,
the trimming signal is indicative of a trimming value of the clock frequency, and
the clock frequency is changed based on the trimming signal.
19 . An integrated sensor, comprising:
a clock configured to provide a clock signal having a clock frequency;
a first digital detector configured to:
detect a power grid signal; and
generate a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and
a timing monitor configured to:
receive the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal in order to compare the reference digital signal with the nominal signal; and
in response to the comparison, provide an error signal indicative of a timing error between the reference digital signal and the nominal signal,
the timing monitor including a trimming module configured to:
receive the error signal; and
provide a trimming signal configured to compensate for the timing error; and
a second digital detector configured to:
detect a physical quantity;
provide an output digital signal indicative of the detected physical quantity and having a sample rate which is a function of the clock frequency;
receive the trimming signal; and
in response to the trimming signal being received, modify the sample rate of the output digital signal.
20 . An integrated sensor, comprising:
a clock configured to provide a clock signal having a clock frequency;
a digital detector configured to:
detect a power grid signal; and
generate a reference digital signal indicative of the power grid signal and having a sample rate which is a function of the clock frequency; and
a timing monitor configured to:
receive the reference digital signal and a nominal signal indicative of a nominal timing of the reference digital signal in order to compare the reference digital signal with the nominal signal; and
in response to the comparison, provide an error signal indicative of a timing error between the reference digital signal and the nominal signal,
the timing monitor including a trimming module configured to:
receive the error signal; and
provide a trimming signal configured to compensate for the timing error,
the clock is configured to:
receive the trimming signal; and
in response to the trimming signal being received, modify the clock frequency of the clock signal.