Low power architecture for chiplets
A method for communicating test information, includes providing a data stream to a circuit block that is implemented on a semiconductor die, demultiplexing data channels from the data stream, multiplexing the data channels to obtain a modified data stream after test information collected from a plurality of sections of the circuit block has been inserted into one or more data channels allocated to at least one section of the circuit block by corresponding embedded distributed test (EDT) circuits implemented in the at least one section of the circuit block, and transmitting the modified data stream to another circuit block implemented on the semiconductor die.
1 . An integrated circuit device, comprising:
two or more semiconductor dice, each semiconductor die comprising:
a circuit block configured to implement a function of the integrated circuit device, wherein the circuit block is partitioned into a plurality of embedded distributed test (EDT) sections; and
a plurality of EDT circuits, wherein at least one EDT circuit is provided in each EDT section in the plurality of EDT sections, and wherein each of the plurality of EDT circuits is configured to collect test information from a corresponding EDT section; and
a central EDT circuit provided in the circuit block and configured to:
distribute a plurality of EDT channels from a received EDT data stream among the plurality of EDT circuits such that each EDT circuit receives a subset of EDT channels allocated to a corresponding EDT section; and
receive an input from each EDT circuit in the plurality of EDT circuits and to provide an output EDT data stream by multiplexing the input received from the each EDT circuit with inputs received from other EDT circuits in the plurality of EDT circuits.
2 . The integrated circuit device of claim 1 , wherein each EDT circuit comprises:
a demultiplexer configured to extract one or more channels in a multiplexed EDT data stream that are allocated to the each EDT circuit; and
a multiplexer configured to recombine the one or more channels that are allocated to the each EDT circuit into the output EDT data stream.
3 . The integrated circuit device of claim 1 , wherein the central EDT circuit is configured to:
distribute a plurality of channels in a multiplexed EDT data stream to the plurality of EDT circuits, wherein
the test information collected by each EDT circuit is inserted into a channel that is distributed to the each EDT circuit.
4 . The integrated circuit device of claim 3 , wherein the central EDT circuit is further configured to combine channels output by the plurality of EDT circuits to obtain the output EDT data stream.
5 . The integrated circuit device of claim 1 , wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections.
6 . The integrated circuit device of claim 1 , wherein the circuit block is partitioned into the plurality of EDT sections based on a distribution of interconnects associated with the plurality of EDT circuits.
7 . The integrated circuit device of claim 1 , wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the plurality of EDT circuits.
8 . The integrated circuit device of claim 1 , wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the plurality of EDT circuits to a predefined maximum.
9 . The integrated circuit device of claim 1 , further comprising:
a decoder configured to decompress a plurality of channels that includes channels modified by the plurality of EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream.
10 . A method for communicating test information, comprising:
providing an embedded distributed test (EDT) data stream to a circuit block that is implemented on a semiconductor die, wherein the circuit block is partitioned into a plurality of EDT sections and at least one EDT circuit is provided in each EDT section in the plurality of EDT sections;
demultiplexing EDT data channels from the EDT data stream at a central EDT circuit;
distributing, at the central EDT circuit, the EDT data channels among the plurality of EDT sections such that each EDT circuit receives a subset of the EDT data channels allocated to a corresponding EDT section;
multiplexing the EDT data channels at the central EDT circuit to obtain a modified EDT data stream after test information collected by the central EDT circuit from each of the plurality of EDT sections has been inserted into one or more EDT data channels allocated to the plurality of EDT sections of the circuit block by corresponding EDT circuits; and
transmitting the modified EDT data stream from the central EDT circuit to another circuit block implemented on the semiconductor die.
11 . The method of claim 10 , wherein each EDT circuit is configured to:
extract at least one EDT data channel allocated to the each EDT circuit; and
use a multiplexer to recombine the at least one EDT data channel allocated to the each EDT circuit into an output EDT data stream.
12 . The method of claim 10 , further comprising:
distributing a portion of the EDT data channels to each EDT circuit based on location of the circuit block and an association between the circuit block and the each EDT circuit.
13 . The method of claim 10 , wherein the central EDT circuit is configured to distribute the EDT data channels in the EDT data stream among the EDT circuits.
14 . The method of claim 13 , wherein the central EDT circuit is further configured to combine output EDT data channels provided by the EDT circuits to obtain the modified EDT data stream.
15 . The method of claim 10 , wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections.
16 . The method of claim 10 , wherein the circuit block is partitioned into the plurality of EDT sections based on a distribution of interconnects associated with the EDT circuits.
17 . The method of claim 10 , wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits.
18 . The method of claim 10 , wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the EDT circuits to a predefined maximum.
19 . The method of claim 10 , further comprising:
decompressing a plurality of channels that include the EDT data channels modified by the EDT circuits, wherein the EDT channels is extracted from a broadcast EDT data stream.
20 . An apparatus, comprising:
means for providing a data stream to a circuit block that is implemented on a semiconductor die, wherein the circuit block is partitioned into a plurality of embedded distributed test (EDT) sections and at least one EDT circuit is provided in each EDT section in the plurality of EDT sections and to distribute data channels from the data stream among the plurality of EDT sections such that each EDT circuit receives a subset of EDT channels allocated to a corresponding EDT section;
means for demultiplexing the data channels from the data stream, including a central EDT circuit that is configured to receive an input from the at least one EDT circuit in each EDT section; and
means for multiplexing the data channels to obtain a modified data stream after test information collected from the plurality of EDT sections has been inserted into one or more data channels allocated to the plurality of EDT sections of the circuit block by corresponding EDT circuits, wherein the test information is received by the central EDT circuit in inputs provided by the at least one EDT circuit in each EDT section in the plurality of EDT sections,
wherein the modified data stream is transmitted by the central EDT circuit to another circuit block implemented on the semiconductor die.
21 . The apparatus of claim 20 , wherein each EDT circuit is configured to:
extract at least one data channel allocated to the each EDT circuit; and
use a multiplexer to recombine the at least one data channel allocated to the each EDT circuit into an output EDT data stream.
22 . The apparatus of claim 20 , further comprising:
means for distributing a portion of the data channels to each EDT circuit based on location of the circuit block and an association between the circuit block and the each EDT circuit.
23 . The apparatus of claim 20 , wherein the central EDT circuit is configured to distribute the data channels in the data stream among the EDT circuits.
24 . The apparatus of claim 23 , wherein the central EDT circuit is further configured to combine output channels provided by the EDT circuits to obtain the modified data stream.
25 . The apparatus of claim 20 , wherein the circuit block includes multiple voltage domains, each voltage domain corresponding to one of the plurality of EDT sections.
26 . The apparatus of claim 20 , wherein the circuit block is partitioned into the plurality of EDT sections based on a distribution of interconnects associated with the EDT circuits.
27 . The apparatus of claim 20 , wherein the circuit block is partitioned into the plurality of EDT sections based on circuit density associated with the EDT circuits.
28 . The apparatus of claim 20 , wherein the circuit block is partitioned into the plurality of EDT sections to limit a number of isolation clamps associated with the EDT circuits to a predefined maximum.
29 . The apparatus of claim 20 , further comprising:
means for decompressing a plurality of channels that include channels modified by the EDT circuits, wherein the plurality of channels is extracted from a broadcast EDT data stream.