Architecture for testing multiple scan chains

1 . A test system for serially testing N number of finite state machine circuits using N number of scan chains, where N is an integer greater than one, each scan chain coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto, each scan chain having M number of input terminals and one output terminal, where M is an integer greater than one, the test system comprising:

a dispatcher input interface comprising:

a plurality of flip-flops arranged in series, wherein an output of each flip-flop other than a last flip-flop is coupled to a data input of a next flip-flop and a clock terminal of each flip-flop is coupled to a clock signal, wherein the plurality of flip-flops is configured to detect two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of the dispatcher input interface,

a plurality of AND gates coupled to each other and the plurality of flip-flops, wherein the plurality of AND gates is configured to generate a dispatch enable signal based on outputs of the plurality of the flip-flops, the dispatch enable signal indicating entry into the configuration mode,

M number of input terminals, and

N sets of output terminals, each of the N sets of output terminals comprising M number of output terminals coupled to the M number of input terminals of an associated scan chain; and

a dispatcher output interface having N number of input terminals and one output terminal, wherein the output terminal of each scan chain is coupled to one of the N number of input terminals of the dispatcher output interface.

2 . The test system of claim 1 , wherein the dispatcher input interface is configured to:

receive a test input signal indicating the scan chain to be selected for testing the finite state machine circuit coupled to the scan chain; and

receive one or more logic level high shift enable signals or reset signals to end the configuration mode of the dispatcher input interface.

3 . The test system of claim 2 , wherein the dispatcher input interface is configured to:

forward scan signals for testing the finite state machine circuit coupled to the selected scan chain during the configuration mode of the dispatcher input interface.

4 . The test system of claim 3 , wherein the dispatcher output interface is configured to receive an output signal corresponding to the result of the testing at the output terminal of the dispatcher output interface.

5 . The test system of claim 3 , wherein, in the plurality of flip-flops, a data input of a first flip-flop receives the two or more consecutive logic level low shift enable signals or reset signals, wherein the plurality of AND gates comprises:

a first AND gate having inverted inputs, each inverted input of the first AND gate coupled to an output of one of the plurality of flip-flops;

a second AND gate having a first input coupled to an output of the first AND gate, a second input of the second AND gate receiving the test input signal;

a third AND gate having a first input coupled to the output of the first AND gate, a second input of the third AND gate receiving the clock signal; and

a fourth AND gate having a first inverted input coupled to the output of the first AND gate, a second input of the fourth AND gate receiving the test input signal,

wherein the dispatcher input interface comprises:

a third flip-flop having a data input coupled to an output of the second AND gate, a clock terminal of the third flip-flop coupled to an output of the third AND gate;

an encoder circuit having an input coupled to an output of the third flip-flop, the encoder circuit configured to forward the scan chain signals for testing the finite state machine circuit coupled to the selected scan chain based on a signal at the input of the encoder circuit, wherein the encoder circuit disables the forwarding of the scan chain signals for other scan chains not under test; and

a demultiplexer having an input coupled to an output of the fourth AND gate, a selection terminal of the demultiplexer coupled to the output of the third flip-flop, an output of the demultiplexer coupled to a test input of a corresponding scan chain of M number of scan chains.

6 . The test system of claim 1 , wherein the dispatcher output interface comprises a multiplexer, wherein input terminals of the multiplexer are coupled to an output of a scan chain, wherein the multiplexer feeds an output signal from a scan chain under test to an output terminal of the multiplexer, and wherein the output signal is compared to an expected value to determine a status of the finite state machine circuit coupled to the scan chain under test.

7 . The test system of claim 1 , wherein the finite state machine circuits are asynchronous.

8 . A method for serially testing N number of finite state machine circuits using N number of scan chains, where N is an integer greater than one, each scan chain coupled to a finite state machine circuit to test the finite state machine circuit coupled thereto, each scan chain having M number of input terminals and one output terminal, where M is an integer greater than one, the method comprising:

receiving two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of a dispatcher input interface, the dispatcher input interface comprising:

a plurality of flip-flops arranged in series, wherein an output of each flip-flop other than a last flip-flop is coupled to a data input of a next flip-flop and a clock terminal of each flip-flop is coupled to a clock signal, wherein the plurality of flip-flops is configured to detect two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of the dispatcher input interface,

a plurality of AND gates coupled to each other and the plurality of flip-flops, wherein the plurality of AND gates is configured to generate a dispatch enable signal based on outputs of the plurality of the flip-flops, the dispatch enable signal indicating entry into the configuration mode,

M number of input terminals, and

N sets of output terminals, each of the N sets of output terminals comprising M number of output terminals coupled to the M number of input terminals of an associated scan chain;

receiving a test input signal indicating the scan chain to be selected for testing the finite state machine circuit coupled to the scan chain; and

receiving one or more logic level high shift enable signals or reset signals to end the configuration mode of the dispatcher input interface.

9 . The method of claim 8 , further comprising receiving an output signal corresponding to the result of the testing at an output terminal of a dispatcher output interface, the dispatcher output interface having N number of input terminals and one output terminal, wherein the output terminal of each scan chain is coupled to one of the N number of input terminals of the dispatcher output interface.

10 . The method of claim 8 , further comprising forwarding scan signals, by the dispatcher input interface, for testing a finite state machine circuit coupled to the selected scan chain during the configuration mode of the dispatcher input interface.

11 . The method of claim 8 , wherein an output of each scan chain is coupled to a dispatcher output interface, the dispatcher output interface comprising a multiplexer, wherein input terminals of the multiplexer are coupled to an output of a scan chain, the method further comprising:

feeding, by the multiplexer, an output signal from a scan chain under test to an output terminal of the multiplexer; and

comparing the output signal to an expected value to determine a status of the finite state machine circuit coupled to the scan chain under test.

12 . The method of claim 8 , wherein, in the plurality of flip-flops, a data input of a first flip-flop receives the two or more consecutive logic level low shift enable signals or reset signals, wherein the plurality of AND gates comprises:

a first AND gate having inverted inputs, each inverted input of the first AND gate coupled to an output of one of the plurality of flip-flops;

a second AND gate having a first input coupled to an output of the first AND gate, a second input of the second AND gate receiving the test input signal;

a third AND gate having a first input coupled to the output of the first AND gate, a second input of the third AND gate receiving the clock signal; and

a fourth AND gate having a first inverted input coupled to the output of the first AND gate, a second input of the fourth AND gate receiving the test input signal,

wherein the dispatcher input interface comprises:

a third flip-flop having a data input coupled to an output of the second AND gate, a clock terminal of the third flip-flop coupled to an output of the third AND gate;

an encoder circuit having an input coupled to an output of the third flip-flop; and

a demultiplexer having an input coupled to an output of the fourth AND gate, a selection terminal of the demultiplexer coupled to the output of the third flip-flop, an output of the demultiplexer coupled to a test input of a corresponding scan chain of M number of scan chains.

13 . The method of claim 12 , further comprising forwarding, by the encoder circuit, scan chain signals for testing the finite state machine circuit coupled to the selected scan chain based on a signal at the input of the encoder circuit, wherein the encoder circuit disables the forwarding of the scan chain signals for other scan chains not under test.

14 . The method of claim 8 , wherein the finite state machine circuits are asynchronous.

15 . A device, comprising:

N number of asynchronous finite state machine circuits, where N is an integer greater than one;

N number of scan chains, each scan chain coupled to an asynchronous finite state machine circuit to test the asynchronous finite state machine circuit coupled thereto, each scan chain having M number of input terminals and one output terminal, where M is an integer greater than one;

a dispatcher input interface comprising:

a plurality of flip-flops arranged in series, wherein an output of each flip-flop other than a last flip-flop is coupled to a data input of a next flip-flop and a clock terminal of each flip-flop is coupled to a clock signal, wherein the plurality of flip-flops is configured to detect two or more consecutive logic level low shift enable signals or reset signals to initiate a configuration mode of the dispatcher input interface,

a plurality of AND gates coupled to each other and the plurality of flip-flops, wherein the plurality of AND gates is configured to generate a dispatch enable signal based on outputs of the plurality of the flip-flops, the dispatch enable signal indicating entry into the configuration mode,

M number of input terminals, and

N sets of output terminals, each of the N sets of output terminals comprising M number of output terminals coupled to the M number of input terminals of an associated scan chain; and

a dispatcher output interface having N number of input terminals and one output terminal, wherein the output terminal of each scan chain is coupled to one of the N number of input terminals of the dispatcher output interface.

16 . The device of claim 15 , wherein the dispatcher input interface is configured to:

receive a test input signal indicating the scan chain to be selected for testing the asynchronous finite state machine circuit coupled to the scan chain; and

receive one or more logic level high shift enable signals or reset signals to end the configuration mode of the dispatcher input interface.

17 . The device of claim 16 , wherein the dispatcher input interface is configured to:

forward scan signals for testing the asynchronous finite state machine circuit coupled to the selected scan chain during the configuration mode of the dispatcher input interface.

18 . The device of claim 17 , wherein the dispatcher output interface is configured to receive an output signal corresponding to the result of the testing at the output terminal of the dispatcher output interface.

19 . The device of claim 18 , wherein, in the plurality of flip-flops, a data input of a first flip-flop receives the two or more consecutive logic level low shift enable signals or reset signals, wherein the plurality of AND gates comprises:

a first AND gate having inverted inputs, each inverted input of the first AND gate coupled to an output of one of the plurality of flip-flops;

a second AND gate having a first input coupled to an output of the first AND gate, a second input of the second AND gate receiving the test input signal;

a third AND gate having a first input coupled to the output of the first AND gate, a second input of the third AND gate receiving the clock signal; and

a fourth AND gate having a first inverted input coupled to the output of the first AND gate, a second input of the fourth AND gate receiving the test input signal,

wherein the dispatcher input interface comprises:

a third flip-flop having a data input coupled to an output of the second AND gate, a clock terminal of the third flip-flop coupled to an output of the third AND gate;

an encoder circuit having an input coupled to an output of the third flip-flop, the encoder circuit configured to forward the scan chain signals for testing the asynchronous finite state machine circuit coupled to the selected scan chain based on a signal at the input of the encoder circuit, wherein the encoder circuit disables the forwarding of the scan chain signals for other scan chains not under test; and

a demultiplexer having an input coupled to an output of the fourth AND gate, a selection terminal of the demultiplexer coupled to the output of the third flip-flop, an output of the demultiplexer coupled to a test input of a corresponding scan chain of M number of scan chains.

20 . The device of claim 19 , wherein the dispatcher output interface comprises a multiplexer, wherein input terminals of the multiplexer are coupled to an output of a scan chain, wherein the multiplexer feeds an output signal from a scan chain under test to an output terminal of the multiplexer, and wherein the output signal is compared to an expected value to determine a status of the asynchronous finite state machine circuit coupled to the scan chain under test.