Semiconductor device with waveguide structure and method for manufacturing the same
A method for manufacturing a semiconductor device includes: forming a first waveguide structure and a second waveguide structure on a substrate in which the first waveguide structure and the second waveguide structure is spaced apart from each other by a recess; conformally forming an un-doped dielectric layer to cover the first and second waveguide structures and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and forming a doped filling layer to fill the gap.
1 . A method for manufacturing a semiconductor device comprising:
forming a first waveguide structure and a second waveguide structure on a substrate, the first waveguide structure and the second waveguide structure being spaced apart from each other by a recess;
conformally forming an un-doped dielectric layer to cover the first waveguide structure and the second waveguide structure and to form a gap between two corresponding portions of the un-doped dielectric layer laterally covering the first waveguide structure and the second waveguide structure, respectively; and
forming a doped filling layer to fill the gap,
wherein the recess has a width which decreases gradually and then increases gradually along a depth direction from an upper end toward a lower end of the recess, such that a smallest width (D) of the recess is formed in a middle portion of the recess.
2 . The method according to claim 1 , wherein the doped filling layer is formed by sub-atmospheric chemical vapor deposition.
3 . The method according to claim 1 , wherein the doped filling layer is formed using a silicon-containing precursor, an oxygen-containing precursor, and at least one of a boron-containing precursor and a phosphorus-containing precursor.
4 . The method according to claim 3 , wherein the silicon-containing precursor includes tetraethyl orthosilicate.
5 . The method according to claim 3 , wherein the oxygen-containing precursor includes oxygen gas, ozone, or a combination thereof.
6 . The method according to claim 3 , wherein the boron-containing precursor includes triethyl borate.
7 . The method according to claim 3 , wherein the phosphorus-containing precursor includes triethyl phosphate.
8 . A method for manufacturing a semiconductor device comprising:
forming a waveguide-forming material layer on a substrate;
patterning the waveguide-forming material layer to simultaneously form a first waveguide structure and a second waveguide structure on the substrate, the first waveguide structure and the second waveguide structure being spaced apart from each other by a recess;
conformally forming an un-doped dielectric layer to cover the first waveguide structure and the second waveguide structure, the un-doped dielectric layer including a lower portion disposed on the substrate, two upper portions respectively disposed on the first waveguide structure and the second waveguide structure, and two interconnecting portions, each of which interconnects the lower portion and a corresponding one of the two upper portions and laterally covers a corresponding one of the first waveguide structure and the second waveguide structure so as to form a gap between the two interconnecting portions;
forming a doped filling layer to fill the gap; and
removing an upper portion of the doped filling layer and the two upper portions of the un-doped dielectric layer over the first waveguide structure and the second waveguide structure.
9 . The method according to claim 8 , wherein the recess has a depth ranging from 2 μm to 4 μm.
10 . The method according to claim 8 , wherein the recess has a width ranging from 0.6 μm to 20 μm.
11 . The method according to claim 8 , wherein the recess has an aspect ratio which is greater than 0 and up to 10.
12 . The method according to claim 8 , wherein the recess has a width which is the same along a depth direction from an upper end toward a lower end of the recess.
13 . The method according to claim 8 , wherein the recess has a width which decreases gradually and then increases gradually along a depth direction from an upper end toward a lower end of the recess, such that a smallest width (D) of the recess is formed in a middle portion of the recess.
14 . The method according to claim 13 , wherein the recess has a bottom surface having a width (C), an undercut ratio defined as a difference value between C and D divided by 2 being greater than 0 nm and up to 100 nm.
15 . The method according to claim 8 , wherein the recess has a width which decreases gradually along a depth direction from an upper end toward a lower end of the recess.
16 . The method according to claim 8 , wherein a sidewall angle is formed between a sidewall surface and a bottom surface of each of the first waveguide structure and the second waveguide structure, the sidewall angle being greater than 0° and up to 90°.
17 . A semiconductor device comprising:
a substrate;
a first waveguide structure and a second waveguide structure disposed on the substrate; and
a spacer disposed on the substrate to separate the first waveguide structure from the second waveguide structure and including:
a doped dielectric body disposed between the first waveguide structure and the second waveguide structure, and
an un-doped dielectric layer disposed to separate the doped dielectric body from the first waveguide structure and the second waveguide structure,
wherein the spacer directly interfaces the first waveguide structure and the second waveguide structure.
18 . The semiconductor device according to claim 17 , wherein the doped dielectric body includes a dielectric material doped with a dopant selected from boron, phosphorus, or a combination thereof.
19 . The semiconductor device according to claim 18 , wherein the doped dielectric body includes boron in a content of greater than 0 wt % and up to 20 wt % and phosphorus in a content of greater than 0 wt % and up to 20 wt %.
20 . The semiconductor device according to claim 17 , further comprising a dielectric layer disposed on the substrate and directly interfacing the first waveguide structure and the second waveguide structure.