IP Library Granted Patent US 12669644
Granted Patent B2
US 12669644 · App. 17/710,690 · Granted Jun 30, 2026

Designs of thermal insulation for micro-ring resonator (MRR) in on-cavity pic (OCPIC) to achieve effective thermal tuning

Inventors: Chia-Pin Chiu (Tempe, AZ); Kaveh Hosseini (Livermore, CA); Omkar Karhade (Chandler, AZ)
Assignee: Intel Corporation
G02B6/12007G02B6/136G02B2006/12061G02B6/29338G02B6/29395
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Quick Facts
Patent No.
US 12669644
App. No.
17/710,690
Granted
Jun 30, 2026
Kind
B2
Abstract

Embodiments disclosed herein include optoelectronic systems and methods of forming such systems. In an embodiment, an optoelectronic system comprises a first substrate, a second substrate over the first substrate, and a micro-ring resonator (MRR) over the second substrate. In an embodiment, a heater is integrated into the MRR, a cladding is over the MRR, and an opening is through the first substrate and the second substrate to expose a bottom surface of the MRR.

Claims (39)

1 . An optoelectronic system, comprising:

a first substrate;

a second substrate over the first substrate;

a micro-ring resonator (MRR) over the second substrate, wherein the MRR comprises an N-doped layer, a P-doped layer over the N-doped layer, and an N-doped region in the P-doped layer;

a heater integrated into the MRR;

wherein the heater is between the N-doped region and the P-doped region;

a cladding over the MRR; and

an opening through the first substrate and the second substrate to expose a bottom surface of the MRR.

2 . The optoelectronic system of claim 1 , wherein the first substrate comprises silicon and the second substrate comprises an oxide.

3 . The optoelectronic system of claim 1 , wherein the opening continues into the cladding adjacent to sidewalls of the MRR.

4 . The optoelectronic system of claim 3 , wherein the opening continues into the cladding past a top surface of the MRR.

5 . The optoelectronic system of claim 1 , wherein the opening through the first substrate has substantially vertical sidewalls.

6 . The optoelectronic system of claim 1 , wherein the opening through the first substrate has tapered sidewalls.

7 . The optoelectronic system of claim 1 , further comprising:

contacts coupled to a top surface of the MRR.

8 . The optoelectronic system of claim 7 , wherein the contacts are electrically coupled to pads on a top surface of the cladding.

9 . The optoelectronic system of claim 1 , wherein the MRR has a thickness that is approximately 250 nm or less.

10 . A method of forming an optoelectronic system, comprising:

forming a micro-ring resonator (MRR) with a heater on a substrate, wherein the substrate is a silicon on insulator (SOI) substrate with a silicon substrate and an oxide layer over the silicon substrate, wherein a cladding is provided over and around the MRR, wherein the MRR comprises an N-doped layer, a P-doped layer over the N-doped layer, and an N-doped region in the P-doped layer, and wherein the heater is between the N-doped region and the P-doped region;

 applying a mask to a bottom surface of the silicon substrate, wherein an opening of the mask is aligned with the MRR; and

 etching through the silicon substrate and the oxide layer to expose a bottom surface of the MRR.

11 . The method of claim 10 , wherein a width of the opening of the mask is wider than a width of the MRR.

12 . The method of claim 11 , wherein the etching further comprises etching the cladding adjacent to the MRR.

13 . The method of claim 12 , wherein the etching of the cladding extends past a top surface of the MRR.

14 . The method of claim 10 , wherein the etching is a dry etching process.

15 . The method of claim 10 , wherein the etching is a wet etching process.

16 . An optoelectronic system, comprising:

a package substrate;

a photonics integrated circuit (PIC) coupled to the package substrate, wherein the PIC comprises:

a first substrate;

a second substrate over the first substrate;

a micro-ring resonator (MRR) over the second substrate, wherein the MRR comprises an N-doped layer, a P-doped layer over the N-doped layer, and an N-doped region in the P-doped layer;

a heater integrated into the MRR;

wherein the heater is between the N-doped region and the P-doped region;

a cladding over the MRR; and

an opening through the first substrate and the second substrate to expose a bottom surface of the MRR; and

an electronic integrated circuit (EIC) coupled to the PIC.

17 . The optoelectronic system of claim 16 , wherein the opening has vertical sidewalls through the first substrate and the second substrate.

18 . The optoelectronic system of claim 16 , wherein the opening extends into the cladding adjacent to the MRR.