Liquid crystal display device

1 . A liquid crystal display device, comprising:

a substrate having a main surface including a display region and a non-display region positioned out of the display region;

a plurality of gate bus lines positioned in the display region, and extending in a first direction;

a plurality of source bus lines positioned in the display region, extending in a direction intersecting with the plurality of gate bus lines, and including at least one first source bus line, at least one second source bus line, and at least one third source bus line;

a plurality of pixels arranged two-dimensionally in the display region, each pixel of the plurality of pixels surrounded with:

a pair of gate bus lines included in the plurality of gate bus lines and adjacent to each other, and

a pair of source bus lines included in the plurality of source bus lines and adjacent to each other;

at least one source driver disposed in the non-display region;

a plurality of source lead lines connecting the plurality of source bus lines, at one end, to the source driver, the plurality of source lead lines including at least one first source lead line, at least one second source lead line, and at least one third source lead line; and

a plurality of capacitance lines positioned in the display region, each of the plurality of capacitance lines disposed to intersect with the at least one first source bus line and the at least one second source bus line, and connected to a common potential,

wherein:

each of the plurality of capacitance lines has:

a first portion extending in the first direction; and

a plurality of second portions extending, in a direction in which the plurality of source bus lines extend, at intersections with the at least one first source bus line and the at least one second source bus line, the plurality of second portions overlapping the plurality of source bus lines,

the at least one first source lead line is connected to the at least one first source bus line, the at least one second source lead line is connected to the at least one second source bus line, and the at least one third source lead line is connected to the at least one third source bus line,

the at least one second source lead line is longer than the at least one first source lead line, the at least one third source lead line is longer than the at least one second source lead line,

the third source bus line does not intersect with the plurality of capacitance lines, and

an area in which the second source bus line and one of the plurality of capacitance lines overlap each other is smaller than an area in which the first source bus line and one of the plurality of capacitance lines overlap each other.

2 . A liquid crystal display device, comprising:

a substrate having a main surface including a display region and a non-display region positioned out of the display region;

a plurality of gate bus lines positioned in the display region, and extending in a first direction;

a plurality of source bus lines positioned in the display region, extending in a direction intersecting with the plurality of gate bus lines, and including at least one first source bus line and at least one second source bus line;

a plurality of pixels arranged two-dimensionally in the display region, each pixel of the plurality of pixels surrounded with:

a pair of gate bus lines included in the plurality of gate bus lines and adjacent to each other, and

a pair of source bus lines included in the plurality of source bus lines and adjacent to each other;

at least one source driver disposed in the non-display region;

a plurality of source lead lines connecting the plurality of source bus lines, at one end, to the source driver, the plurality of source lead lines including at least one first source lead line and at least one second source lead line; and

a plurality of capacitance lines positioned in the display region, each of the plurality of capacitance lines disposed to intersect with the at least one first source bus line and the at least one second source bus line, and connected to a common potential,

wherein:

each of the plurality of capacitance lines has:

a first portion extending in the first direction; and

a plurality of second portions extending, in a direction in which the plurality of source bus lines extend, at intersections with the at least one first source bus line and the at least one second source bus line, the plurality of second portions overlapping the plurality of source bus lines,

the at least one first source lead line is connected to the at least one first source bus line, and the at least one second source lead line is connected to the at least one second source bus line,

the at least one second source lead line is longer than the at least one first source lead line, and

an area in which the second source bus line and one of the plurality of capacitance lines overlap each other is smaller than an area in which the first source bus line and one of the plurality of capacitance lines overlap each other,

among the plurality of second portions of each of the plurality of capacitance lines, in a case that a second portion overlapping the second source bus line has a length along the second source bus line, and a second portion overlapping the first source bus line has a length along the first source bus line, the length along the second source bus line is shorter than the length along the first source bus line.

3 . The liquid crystal display device according to claim 1 , further comprising:

a plurality of dummy wires arranged in the display region,

wherein:

each of the plurality of dummy wires extends in the first direction, is adjacent to the third source bus line, and is a direct extension of one of the plurality of the capacitance lines, and

the plurality of dummy wires does not intersect with any of the plurality of source bus lines.

4 . A liquid crystal display device, comprising:

a substrate having a main surface including a display region and a non-display region positioned out of the display region;

a plurality of gate bus lines positioned in the display region, and extending in a first direction;

a plurality of source bus lines positioned in the display region, extending in a direction intersecting with the plurality of gate bus lines, and including at least one first source bus line, at least one second source bus line, and at least one third source bus line;

a plurality of pixels arranged two-dimensionally in the display region, each pixel of the plurality of pixels surrounded with:

a pair of gate bus lines included in the plurality of gate bus lines and adjacent to each other, and

a pair of source bus lines included in the plurality of source bus lines and adjacent to each other;

at least one source driver disposed in the non-display region;

a plurality of source lead lines connecting the plurality of source bus lines, at one end, to the source driver, including at least one first source lead line, at least one second source lead line, and at least one third source led line; and

a plurality of capacitance lines positioned in the display region, each of the plurality of capacitance lines disposed to intersect with the at least one first source bus line and the at least one second source bus line, and connected to a common potential,

wherein:

each of the plurality of capacitance lines has:

a first portion extending in the first direction; and

a plurality of second portions extending, in a direction in which the plurality of source bus lines extend, at intersections with the at least one first source bus line and the at least one second source bus line, the plurality of second portions overlapping the plurality of source bus lines,

the at least one first source lead line is connected to the at least one first source bus line, the at least one second source lead line is connected to the at least one second source bus line, and the at least one third source lead line is connected to the at least one third source bus line,

the at least one second source lead line is longer than the at least one first source lead line, and the at least one third source lead line is longer than the at least one second source lead line,

an area in which the second source bus line and one of the plurality of capacitance lines overlap each other is smaller than an area in which the first source bus line and one of the plurality of capacitance lines overlap each other,

the first portion of each of the plurality of capacitance lines extends to intersect with the third source bus line, and

an area in which the third source bus line and one of the plurality of capacitance lines overlap each other is smaller than an area in which the second source bus line and one of the plurality of capacitance lines overlap each other.

5 . The liquid crystal display device according to claim 4 ,

wherein, at an intersection with the third source bus line, each of the plurality of capacitance lines does not have the second portions extending in a direction in which the third source bus line extends.

6 . The liquid crystal display device according to claim 1 ,

wherein:

each of the plurality of pixels includes:

a pixel electrode; and

a thin-film transistor (TFT) connected to the pixel electrode, the pixel electrode has a plurality of opening portions shaped into slits, and extending along the plurality of source bus lines, and

each first portion of the plurality of capacitance lines is disposed in the display region to overlap bends of the plurality of opening portions included in the pixel electrodes of pixels included in the plurality of pixels that are arranged in the first direction.

7 . The liquid crystal display device according to claim 6 ,

wherein each of the plurality of opening portions comprises:

a first bending portion and a second bending portion, the first bending portion disposed near one of the pair of gate bus lines, and the second bending portion disposed near the other one of the pair of gate bus lines; and

a third bending portion positioned between the first bending portion and the second bending portion.

8 . The liquid crystal display device according to claim 7 ,

wherein each of the plurality of capacitance lines is disposed in the display region to overlap either the first bending portion or the second bending portion of each of the pixels arranged in the first direction.

9 . The liquid crystal display device according to claim 7 ,

wherein each of the plurality of capacitance lines is disposed in the display region to overlap the third bending portion of each of the plurality of pixels arranged in the first direction, and

each of the plurality of second portions extends from the first portion toward the first bending portion and the second bending portion.

10 . The liquid crystal display device according to claim 1 , further comprising:

a common electrode disposed in the display region to overlap a pixel electrode,

wherein the plurality of capacitance lines is electrically connected to the common electrode in the display region.

11 . The liquid crystal display device according to claim 10 ,

wherein, in the display region, each of the plurality of capacitance lines is electrically connected to the common electrode at a plurality of positions.

12 . The liquid crystal display device according to claim 1 ,

wherein the plurality of capacitance lines extends to reach the non-display region, and

in the non-display region, the plurality of capacitance lines is connected to a wire that supplies the common potential.

13 . The liquid crystal display device according to claim 1 ,

wherein the plurality of capacitance lines and the plurality of gate bus lines include a same metal layer.

14 . The liquid crystal display device according to claim 12 ,

wherein at least any two of the at least one first source lead line, the at least one second source lead line, and the at least one third source lead line partially overlap one another in a plan view.