Reduction of bandgap voltage variation in an integrated circuit

1 . A circuit for reducing bandgap voltage variation comprising:

an operational amplifier;

a first transistor configured to receive an output of the operational amplifier;

a second transistor operatively connected to the first transistor, the second transistor configured to receive the output of the operational amplifier; and

a digital calibration engine operatively connected with the operational amplifier, wherein the digital calibration engine trims an input of the operational amplifier to address a mismatch between the first transistor and the second transistor.

2 . The circuit of claim 1 , wherein the digital calibration engine is configured to address the mismatch between the first transistor and the second transistor while an operational amplifier offset is corrected simultaneously.

3 . The circuit of claim 1 , further comprising:

a first bipolar junction transistor operatively connected to an input of the operational amplifier.

4 . The circuit of claim 3 , further comprising:

a second bipolar junction transistor operatively connected to an input of the operational amplifier.

5 . The circuit of claim 4 , further comprising:

a third transistor and a resistor configured to activate the first transistor and second transistor.

6 . The circuit of claim 2 , wherein the simultaneously correcting occurs in a single trim.

7 . The circuit of claim 5 , wherein activating the first transistor and the second transistor occurs during a calibration mode.

8 . The circuit of claim 5 , further comprising:

a first switch located between the second transistor and the third transistor.

9 . The circuit of claim 4 , wherein the first bipolar junction transistor and the second bipolar junction transistor have the same characteristics.

10 . The circuit of claim 1 , further comprising:

a second switch located between the operational amplifier and the first transistor and the second transistor.

11 . A method for reducing bandgap voltage variation comprising:

providing an operational amplifier;

receiving an output of the operational amplifier at a first transistor;

operatively connecting a second transistor with the first transistor, the second transistor configured to receive the output of the operational amplifier; and

trimming, using a digital calibration engine operatively connected with the operational amplifier, an input of the operational amplifier to address a mismatch between the first transistor and the second transistor.

12 . The method of claim 11 , further comprising:

simultaneously correcting a mismatch between the first transistor and the second transistor and an operational amplifier offset.

13 . The method of claim 11 , further comprising:

operatively connecting a first bipolar junction transistor to an input of the operational amplifier.

14 . The method of claim 13 , further comprising:

operatively connecting a second bipolar junction transistor to an input of the operational amplifier.

15 . The method of claim 14 , further comprising:

activating the first transistor and second transistor using a third transistor and a resistor.

16 . The method of claim 12 , wherein the simultaneously correcting occurs in a single trim.

17 . The method of claim 15 , wherein activating the first transistor and the second transistor occurs during a calibration mode.

18 . The method of claim 15 , further comprising:

providing a first switch between the second transistor and the third transistor.

19 . The method of claim 14 , wherein the first bipolar junction transistor and the second bipolar junction transistor have the same characteristics.

20 . The method of claim 11 , further comprising:

providing a second switch between the operational amplifier and the first transistor and the second transistor.