IP Library › Granted Patent US 12,669,842

Granted Patent B2

US 12,669,842 · App. 18/913,445 · Granted Jun 30, 2026

Reducing phase error associated with physical layer clock switchover

Inventors: Anthony Lawrence Duong (Framingham, MA); Satish Gopalakrishnan (Fremont, CA); Srinivas Pattangi Seshadri (Fremont, CA); Suresh Namadev Mulekar (Fremont, CA); Kamatchi S. Gopalakrishnan (Dublin, CA)

Assignee: Hewlett Packard Enterprise Development LP

G06F1/08 G06F1/14

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Quick Facts

Patent No.: US 12,669,842
App. No.: 18/913,445
Granted: Jun 30, 2026
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A node determines a frequency offset between a physical layer clock and a local oscillator clock, wherein the node uses the physical layer clock as a clock source for a local time counter. The node tunes, based on the frequency offset, a frequency of the local oscillator clock. The node then identifies an issue that is associated with the physical layer clock and thereby causes the local oscillator clock to be the clock source for the local time counter. The node identifies, after causing the local oscillator clock to be the clock source for the local time counter, that the issue that is associated is resolved or that a time interval has elapsed, and thereby causes the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

Claims (70)

1 . A method, comprising:

determining, by a node, a frequency offset between a physical layer clock and a local oscillator clock,

wherein the node uses the physical layer clock as a clock source for a local time counter;

tuning, by the node and based on the frequency offset, a frequency of the local oscillator clock;

identifying, by the node and after tuning the frequency of the local oscillator clock, an issue that is associated with the physical layer clock; and

causing, by the node and based on identifying the issue that is associated with the physical layer clock, the local oscillator clock to be the clock source for the local time counter.

2 . The method of claim 1 , further comprising:

identifying, after causing the local oscillator clock to be the clock source for the local time counter, that the issue that is associated with the physical layer clock is resolved; and

causing, based on identifying that the issue that is associated with the physical layer clock is resolved, the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

3 . The method of claim 1 , further comprising:

identifying that a time interval since causing the local oscillator clock to be the clock source for the local time counter has elapsed; and

causing, based on identifying that the time interval since causing the local oscillator clock to be the clock source for the local time counter has elapsed, the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

4 . The method of claim 1 , further comprising:

causing, after causing the local oscillator clock to be the clock source for the local time counter, a particular physical layer clock, of the physical layer clock and another physical layer clock, to be the clock source for the local time counter.

5 . The method of claim 4 , further comprising:

determining, based on causing the particular physical layer clock to be the clock source for the local time counter, another frequency offset between the particular physical layer clock and the local oscillator clock; and

retuning, based on the other frequency offset, the frequency of the local oscillator clock.

6 . The method of claim 4 , further comprising:

identifying, by the node and after causing the particular physical layer clock to be the clock source for the local time counter, another issue that is associated with the particular physical layer clock; and

causing, based on identifying the other issue that is associated with the particular physical layer clock, the local oscillator clock to be the clock source for the local time counter again.

7 . The method of claim 1 , wherein identifying the issue that is associated with the physical layer clock comprises at least one of:

determining that a link associated with the physical layer clock is down;

determining that a quality level (QL) of the physical layer clock is degraded; or

receiving an Ethernet synchronization message channel (ESMC) message indicating that the QL of the physical layer clock is degraded.

8 . A node, comprising:

one or more memories; and

one or more processors to:

determine a frequency offset between a physical layer clock and a local oscillator clock,

tune, based on the frequency offset, a frequency of the local oscillator clock;

identify, after tuning the frequency of the local oscillator clock, an issue that is associated with the physical layer clock; and

cause, based on identifying the issue that is associated with the physical layer clock, the local oscillator clock to be a clock source for a local time counter.

9 . The node of claim 8 , wherein the one or more processors are further to:

cause, based on at least one of identifying that the issue that is associated with the physical layer clock is resolved or identifying that a time interval since causing the local oscillator clock to be the clock source for the local time counter has elapsed, the physical layer clock, or another physical layer clock, to be the clock source for the local time counter.

10 . The node of claim 8 , wherein the one or more processors are further to:

cause, after causing the local oscillator clock to be the clock source for the local time counter, a particular physical layer clock, of the physical layer clock and another physical layer clock, to be the clock source for the local time counter.

11 . The node of claim 10 , wherein the one or more processors are further to:

determine, based on causing the particular physical layer clock to be the clock source for the local time counter, another frequency offset between the particular physical layer clock and the local oscillator clock; and

retune, based on the other frequency offset, the frequency of the local oscillator clock.

12 . The node of claim 10 , wherein the one or more processors are further to:

identify, after causing the particular physical layer clock to be the clock source for the local time counter, another issue that is associated with the particular physical layer clock; and

cause, based on identifying the other issue that is associated with the particular physical layer clock, the local oscillator clock to be the clock source for the local time counter again.

13 . The node of claim 8 , further comprising:

an oscillator; and

a direct digital frequency synthesizer (DDFS), wherein:

the local oscillator clock includes the oscillator and the DDFS.

14 . The node of claim 8 , further comprising:

a frequency counter, wherein:

the one or more processors, to determine the frequency offset, are to:

identify, using the frequency counter, a first frequency associated with the physical layer clock;

identify, using the frequency counter, a second frequency associated with the local oscillator clock; and

determine the frequency offset based on the first frequency and the second frequency.

15 . The node of claim 8 , wherein the one or more processors, to tune the frequency of the local oscillator clock, are to:

send, based on the frequency offset, one or more frequency adjustment commands to a direct digital frequency synthesizer (DDFS) associated with the local oscillator clock.

16 . The node of claim 8 , further comprising:

a digital phase-locked loop (DPLL) associated with the physical layer clock, wherein:

the one or more processors, to identify the issue that is associated with the physical layer clock, are to:

determining, using the DPLL, that at least one of:

a link associated with the physical layer clock is down; or

a quality level (QL) of the physical layer clock is degraded.

17 . A non-transitory computer-readable medium storing a set of instructions, the set of instructions comprising:

one or more instructions that, when executed by one or more processors of a node, cause the node to:

tune, based on a frequency offset between a physical layer clock and a local oscillator clock, a frequency of the local oscillator clock;

identify, after tuning the frequency of the local oscillator clock, an issue that is associated with the physical layer clock; and

cause, based on identifying the issue that is associated with the physical layer clock, the local oscillator clock to be a clock source for a local time counter.

18 . The non-transitory computer-readable medium of claim 17 , wherein the one or more instructions further cause the node to:

cause, based on at least one of identifying that the issue that is associated with the physical layer clock is resolved or identifying that a time interval since causing the local oscillator clock to be the clock source for the local time counter has elapsed, the local oscillator clock to cease being the clock source for the local time counter.

19 . The non-transitory computer-readable medium of claim 17 , wherein the one or more instructions further cause the node to:

retune, after causing the local oscillator clock to cease being the clock source for the local time counter, the frequency of the local oscillator clock based on another frequency offset between a particular physical layer clock, of the physical layer clock and another physical layer clock, and the local oscillator clock.

20 . The non-transitory computer-readable medium of claim 19 , wherein the one or more instructions further cause the node to:

cause, after retuning the frequency of the local oscillator clock, the local oscillator clock to be the clock source for the local time counter again.