Synchronizer circuit
A circuit portion receives, at a synchroniser, a signal clocked at a first frequency and outputs a synchronised signal clocked at a second frequency to a bounce-rejection circuit portion. The bounce-rejection circuit portion operates on a plurality of successive samples of the synchronised signal and outputs an output signal. The bounce-rejection circuit portion: changes the output signal from a first value to a second value if a proportion of said plurality of successive samples having said second value is determined to meet a threshold, the threshold being greater than 50% of the plurality of successive samples; otherwise, it maintains the output signal at the first value.
1 . A method of operating a circuit portion, comprising:
receiving, at a synchroniser, a signal clocked at a first frequency;
outputting a synchronised signal clocked at a second frequency to a bounce-rejection circuit portion;
the bounce-rejection circuit portion operating on a plurality of successive samples of the synchronised signal and outputting an output signal, wherein the bounce-rejection circuit portion:
changes the output signal from a first logic value to a second logic value if a proportion of said plurality of successive samples having said second logic value is determined to meet a threshold, wherein the threshold is greater than 50% of the plurality of successive samples; or
otherwise, maintains the output signal at the first logic value.
2 . The method of claim 1 , wherein the threshold is from 60% to 80%.
3 . The method of claim 1 , wherein the threshold is greater than half of an estimated number of metastable samples.
4 . The method of claim 1 , wherein the threshold is equal to at least the estimated number of metastable samples plus one, all divided by two.
5 . The method of claim 1 , wherein the bounce-rejection circuit portion comprises a plurality of flip flops providing at least some of the plurality of successive samples.
6 . The method of claim 1 , comprising
using a first comparator to compare with its respective input with the number of the plurality of successive samples minus the threshold; and
using a second comparator to compare its respective input to the threshold.
7 . The method of claim 1 , wherein the bounce-rejection circuit portion comprises a or the multiplexer and an output flip flop coupled together, wherein the output flip flop feeds back its output to an input of the multiplexer.
8 . The method of claim 5 , comprising providing a first sample of the plurality of successive samples by the synchroniser and providing the remaining samples of the plurality of successive samples by the plurality of flip flops.
9 . The method of claim 6 , comprising:
summing the plurality of successive samples accumulated by an accumulator;
providing the output of the accumulator to the first comparator and the second comparator.
10 . The method of claim 6 , wherein the bounce-rejection circuit portion comprises a multiplexer, the method comprising the multiplexer:
receiving at a first data input of the multiplexer an output from the second comparator;
receiving at a second data input of the multiplexer an output from the bounce rejection circuit portion.
11 . The method of claim 9 , comprising:
the first comparator comparing the output of the accumulator to the number of the plurality of successive samples minus the threshold; and
the second comparator comparing the output of the accumulator to the threshold.
12 . A circuit portion comprising:
a synchroniser comprising:
a signal input for receiving a signal clocked at a first frequency; and
a signal output for outputting a synchronised signal clocked at a second frequency; and
a bounce-rejection circuit portion arranged to receive a synchronised signal from the output of the synchroniser; the bounce-rejection circuit portion being arranged to operate on a plurality of successive samples of the synchronised signal and output an output signal; wherein the bounce-rejection circuit portion is arranged to:
change the output signal from a first logic value to a second logic value if a proportion of said plurality of successive samples having said second logic value is determined to meet a threshold, wherein the threshold is greater than 50% of the plurality of successive samples; or
otherwise, maintain the output signal at the first logic value.
13 . The circuit portion of claim 12 , wherein the threshold is from 60% to 80%.
14 . The circuit portion of claim 12 , wherein the threshold is greater than half of an estimated number of metastable samples.
15 . The circuit portion of claim 12 , wherein the bounce-rejection circuit comprises:
a first comparator arranged to compare its respective input with the number of the plurality of successive samples minus the threshold; and
a second comparator arranged to compare its respective input to the threshold.
16 . The circuit portion of claim 12 , wherein the bounce-rejection circuit portion comprises a multiplexer, the multiplexer being arranged to:
receive at a first data input of the multiplexer an output from the second comparator;
receive at a second data input of the multiplexer an output from the bounce rejection circuit portion.
17 . The circuit portion of claim 12 , wherein the bounce-rejection circuit portion comprises a or the multiplexer and an output flip flop coupled together, wherein the bounce-rejection circuit portion is arranged so that the output flip flop feeds back its output to an input of the multiplexer.
18 . The circuit portion of claim 15 , wherein the bounce-rejection circuit portion comprises an accumulator arranged to sum the plurality of successive samples; and wherein the bounce-rejection circuit portion is arranged to provide the output of the accumulator to the first comparator and the second comparator.
19 . The circuit portion of claim 18 , wherein the bounce-rejection circuit portion is arranged so that:
the first comparator compares the output of the accumulator to the number of the plurality of successive samples minus the threshold; and
the second comparator compares the output of the accumulator to the threshold.
20 . A handshake synchroniser system for synchronising a signal at a clock domain crossing, comprising:
a first clock domain comprising:
a first synchroniser comprising a first signal input for receiving a signal clocked at a second frequency and a first signal output for outputting a synchronised signal clocked at a first frequency; and
a second clock domain comprising:
a second synchroniser comprising a second signal input for receiving a signal clocked at the first frequency and a second signal output for outputting a synchronised signal clocked at the second frequency; and
wherein each of the first and second clock domains comprise a respective bounce-rejection circuit portion arranged to receive a respective synchronised signal from the output of their respective synchroniser; each bounce-rejection circuit portion being arranged to operate on a plurality of successive samples of the respective synchronised signal and output a respective output signal; wherein each bounce-rejection circuit portion is arranged to:
change its output signal from a first logic value to a second logic value if a proportion of said plurality of successive samples having said second logic value is determined to meet a threshold, wherein the threshold is greater than 50% of the plurality of successive samples; or
otherwise, maintain its output signal at the first logic value.