Power-aware transmission of quantum control signals

1 . A method for transmitting control signals from a classical interface of a quantum computer to a quantum processing unit (QPU) of the quantum computer, the quantum computer comprising a plurality of communication channels between the classical interface and the QPU, the method comprising:

receiving, at a central processing unit (CPU) of the classical interface, a digital control signal describing a quantum circuit to be performed by the QPU;

compressing, at the CPU, the digital control signal using a preselected compression scheme;

generating, at the CPU, a sequence staggering configuration indicating one or more delays to be applied to transmission of the compressed digital control signal and a map indicating a number of bits to be transmitted over each of the plurality of communication channels;

outputting, from the CPU to a programable logic unit of the classical interface, the compressed digital control signal, the sequence staggering configuration and the map;

splitting, at the programable logic unit, the compressed digital control signal into one or more sub-streams using the map and sequence staggering configuration; and,

transmitting, from the programable logic unit to the QPU, the one or more sub-streams, wherein the sub-streams are transmitted with the one or more delays.

2 . The method of claim 1 , further comprising:

decompressing, at the QPU, the one or more sub-streams to reconstruct the digital control signal; and,

converting, at the QPU, the digital control signal into a low-level control signal for performing the quantum circuit at the QPU.

3 . The method of claim 1 , further comprising transmitting, from the programable logic unit to the QPU, reconfiguration and/or recalibration instructions.

4 . The method of claim 1 , further comprising:

determining, at the CPU, a number of communication channels over which the compressed digital control signal is to be transmitted; and,

outputting, from the CPU to programable logic unit, the number of communication channels over which the compressed digital control signal is to be transmitted.

5 . The method of claim 1 , wherein the preselected compression scheme is determined by performing the following steps on a classical computing device:

receiving a static power consumption value associated with the QPU and a plurality of dynamic power consumption values associated with a respective plurality of operations performable by the QPU;

determining a plurality of compression schemes implementable by the QPU;

for each of the plurality of compression schemes, calculating, using the static power consumption value and the plurality of dynamic power consumption values, a total power consumption value associated with receiving and decompressing a representative control signal at the QPU using the respective compression scheme; and,

selecting a compression scheme of the plurality of compression schemes having the lowest total power consumption value.

6 . The method of claim 5 , where the operations performable by the QPU comprise decoding a digital 0, decoding a digital 1, reading memory, writing memory, and/or memory latches.

7 . The method of claim 5 , wherein the static power consumption value comprises memory static consumption.

8 . The method of claim 5 , further comprising determining, at the classical computing device, an expected maximum uncompressed bandwidth value.

9 . The method of claim 5 , further comprising receiving, at the classical computing device, an indication of an amount of on-chip memory available at the QPU for decompressing the digital control signals.

10 . The method of claim 5 , further comprising generating, at the classical computing device, digital logic that implements a decoder of the selected compression scheme.

11 . The method of claim 5 , further comprising generating, at the classical computing device, a high-level representation of digital logic that implements a decoder of the selected compression scheme.

12 . The method of claim 5 , further comprising generating, at the classical computing device, software that implements encoding logic for a central processing unit (CPU) of the classical interface and digital logic for a programmable logic unit of the classical interface.

13 . The method of claim 5 , further comprising receiving, at the classical computing device, hardware details associated with the QPU, wherein the total power consumption value is calculated based on the hardware details.

14 . The method of claim 5 , wherein the hardware details comprise a number of communication channels between the classical interface and the QPU, a total number of qubits in the QPU, a distance between neighboring communication channel pins, and/or a connectivity matrix identifying a control logic location for each qubit in the QPU.

15 . The method of claim 5 , wherein the representative control signal comprises a set of circuits that are representative of a typical workload performed by the QPU.

16 . The method of claim 5 , wherein the representative control signal is determined based on a respective likelihood associated with each of a set of native gates of the QPU.

17 . The method of claim 5 , wherein calculating the total power consumption value comprises computing a cost function.

18 . The method of claim 1 , where decompressing the one or more sub-streams comprises buffering, at the QPU, at least one of the one or more sub-streams.

19 . A quantum computing apparatus comprising a classical interface and a quantum processing unit (QPU), wherein the classical interface comprises a central processing unit (CPU) and a programable logic unit,

wherein the CPU is configured to:

receive a digital control signal describing a quantum circuit to be performed by the QPU;

compress the digital control signal using a preselected compression scheme;

generate a sequence staggering configuration indicating one or more delays to be applied to transmission of the compressed digital control signal and a map indicating a number of bits to be transmitted over each of the plurality of communication channels; and

output, to the programable logic unit, the compressed digital control signal, the sequence staggering configuration and the map,

and wherein the programable logic unit is configured to:

split the compressed digital control signal into one or more sub-streams using the map and sequence staggering configuration;

transmit, to the QPU, the one or more sub-streams, wherein the sub-streams are transmitted with the one or more delays.

20 . A non-transitory computer-readable medium comprising instructions which, when executed by a computing computer comprising a quantum processing unit (QPU) and a classical interface, cause the quantum computing apparatus to:

receive, at a central processing unit (CPU) of the classical interface, a digital control signal describing a quantum circuit to be performed by the QPU;

compress, at the CPU, the digital control signal using a preselected compression scheme;

generate, at the CPU, a sequence staggering configuration indicating one or more delays to be applied to transmission of the compressed digital control signal and a map indicating a number of bits to be transmitted over each of the plurality of communication channels;

output, from the CPU to a programable logic unit of the classical interface, the compressed digital control signal, the sequence staggering configuration and the map;

split, at the programable logic unit, the compressed digital control signal into one or more sub-streams using the map and sequence staggering configuration; and,

transmit, from the programable logic unit to the QPU, the one or more sub-streams, wherein the sub-streams are transmitted with the one or more delays.