Multi-mode fusion multiplier

1 . A multi-mode fusion multiplier, configured to receive inputs A[m 1 −1:0] and B[m 2 −1:0] or A0[m 3 −1:0] and B0[m 4 −1:0] and to perform a binary single-multiplication operation A[m 1 −1:0]×B[m 2 −1:0] or an accumulated sum operation of 2N binary multiplications A0[m 3 −1:0]×B0[m 4 −1:0], wherein m 1 ≥2N×m3, m 2 ≥2N×m 4 , N is a positive integer, the multi-mode fusion multiplier comprises P precoders, Q groups of fusion coders, and a compressor, and m 1 , m 2 , m 3 , m 4 , P, and Q are integers greater than 1;

the P precoders are configured to precode a first value based on a single-multiplication indication signal or a multi-multiplication indication signal, to provide a precoding result, wherein the first value is A[m 1 −1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the first value comprises 2N pieces of A0[m 3 −1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of A0[m 3 −1:0] are arranged in a sequence from a low digit weight to a high digit weight;

the Q groups of fusion coders are configured to code the precoding result and a second value, to provide a plurality of partial products, wherein the second value is B[m 2 −1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the second value comprises 2N pieces of B0[m 4 −1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of B0[m 4 −1:0] are arranged in a sequence from a high digit weight to a low digit weight; and

the compressor is configured to compress the plurality of partial products, to provide two accumulated values, wherein a sum of the two accumulated values is a result of the single-multiplication operation or the accumulated sum operation.

2 . The multi-mode fusion multiplier according to claim 1 , wherein when m 1 >2N×m3, first (m 1 −2N×m 3 ) high digit weights in the first value comprise sign bits; and/or when m 2 >2N×m 4 , last (m 2 −2N×m 4 ) low digit weights in the second value comprise invalid bits.

3 . The multi-mode fusion multiplier according to claim 1 , wherein the P precoders comprise an i th precoder, configured to:

determine an i th group of selection signals, an i th group of single-multiplication selection signals, a single-multiplication control signal SCi, and a first multi-multiplication control signal MCi in the precoding result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when i is an even number and 0≤i≤N×m 3 −1; or

determine the i th group of selection signals, the i th group of single-multiplication selection signals, the single-multiplication control signal SCi, a second multi-multiplication control signal MCNi, and a control signal Si in the precoding result based on the single-multiplication indication signal, the multi-multiplication indication signal, and at least two bits in the first value when i is an even number and N×m 3 ≤i≤m 1 −1, wherein

the i th group of selection signals comprises a first selection signal M1Mi and a second selection signal M2Mi, and the i th group of single-multiplication selection signals comprises a first single-multiplication selection signal SM1Mi and a second single-multiplication selection signal SM2Mi.

4 . The multi-mode fusion multiplier according to claim 3 , wherein when i is equal to 0, the at least two bits of the first value comprise a first bit a[0] and a second bit a[1] in the first value; and

the 0 th precoder is configured to perform coding operations comprising:

setting the first selection signal M1Mi to the first bit a[0];

setting the second selection signal M2Mi to 1 when the first bit a[0] is 0 and the second bit a[1] is 1, or setting the second selection signal M2Mi to 0 when the first bit a[0] is not 0 or the second bit a[1] is not 1;

setting the single-multiplication control signal SCi to the second bit a[1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SC0 to 0 when the single-multiplication indication signal is 0;

setting the first multi-multiplication control signal MCi to the second bit a[1] when the multi-multiplication indication signal is 1, or setting the first multi-multiplication control signal MCi to 0 when the multi-multiplication indication signal is 0; and

setting the first single-multiplication selection signal SM1Mi to the first bit a[0] and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0.

5 . The multi-mode fusion multiplier according to claim 3 , wherein when 0<i≤N×m 3 −1, the at least two bits of the first value comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1] in the first value; and

the i th precoder is configured to perform coding operations comprising:

setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i];

setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1];

setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0;

setting the first multi-multiplication control signal MCi to the third bit a[i+1] when the multi-multiplication indication signal is 1, or setting the first multi-multiplication control signal MCi to 0 when the multi-multiplication indication signal is 0; and

setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0.

6 . The multi-mode fusion multiplier according to claim 3 , wherein when i is equal to N×m 3 , the at least two bits of the first value comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1] in the first value; and

the (N×m 3 ) th precoder is configured to perform coding operations comprising:

setting a fourth bit to the first bit a[i−1] when the single-multiplication indication signal is 1, or setting a fourth bit to 0 when the single-multiplication indication signal is 0;

setting the first selection signal M1Mi to 1 when the fourth bit is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the fourth bit is equal to the second bit a[i];

setting the second selection signal M2Mi to 1 when the fourth bit is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the fourth bit is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1];

setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0;

setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indication signal is equal to the third bit a[i+1], or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal is not equal to the third bit a[i+1];

setting the control signal Si to the third bit a[i+1]; and

setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0.

7 . The multi-mode fusion multiplier according to claim 3 , wherein when N×m 3 <i<m 1 −1, the at least two bits of the first value comprise a first bit a[i−1], a second bit a[i], and a third bit a[i+1]; and

the i th precoder is configured to perform coding operations comprising:

setting the first selection signal M1Mi to 1 when the first bit a[i−1] is not equal to the second bit a[i], or setting the first selection signal M1Mi to 0 when the first bit a[i−1] is equal to the second bit a[i];

setting the second selection signal M2Mi to 1 when the first bit a[i−1] is equal to the second bit a[i] and the second bit a[i] is not equal to the third bit a[i+1], or setting the second selection signal M2Mi to 0 when the first bit a[i−1] is not equal to the second bit a[i] or the second bit a[i] is equal to the third bit a[i+1];

setting the single-multiplication control signal SCi to the third bit a[i+1] when the single-multiplication indication signal is 1, or setting the single-multiplication control signal SCi to 0 when the single-multiplication indication signal is 0;

setting the second multi-multiplication control signal MCNi to 0 when the multi-multiplication indication signal is equal to the third bit a[i+1], or setting the second multi-multiplication control signal MCNi to 1 when the multi-multiplication indication signal is not equal to the third bit a[i+1];

setting the first single-multiplication selection signal SM1Mi to the first selection signal M1Mi and setting the second single-multiplication selection signal SM2Mi to the second selection signal M2Mi when the single-multiplication indication signal is 1, or setting both the first single-multiplication selection signal SM1Mi and the second single-multiplication selection signal SM2Mi to 0 when the single-multiplication indication signal is 0; and

setting the control signal Si to the third bit a[i+1].

8 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders comprise a first coder configured to perform coding operation comprising:

setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and a first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and a second bit b[k−1] in the second value are 1; or

setting a partial product p(i, k) to the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and a first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and a second bit b[k−1] in the second value are not both 1.

9 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a second coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the multi-multiplication indication signal and the first bit b[k−1] in the second value are 1 or both the single-multiplication indication signal and the second bit b[k] in the second value are 1, or setting a first intermediate item to 0 when the multi-multiplication indication signal and the first bit b[k−1] in the second value are not both 1 and the single-multiplication indication signal and the second bit b[k] in the second value are not both 1;

setting a second intermediate item to 1 when both the first intermediate item and the first selection signal M1Mi are 1 or both the second selection signal M2Mi and the first bit b[k−1] are 1, or setting a second intermediate item to 0 when the first intermediate item and the first selection signal M1Mi are not both 1 and the second selection signal M2Mi and the first bit b[k−1] are not both 1; and

setting an inversion of the second multi-multiplication control signal MCNi to a partial product p(i, k) when the second intermediate item is 1, or setting the second multi-multiplication control signal MCNi to a partial product p(i, k) when the second intermediate item is 0.

10 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a third coder configured to perform coding operation:

setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1; or

setting a partial product p(i, k) to the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1.

11 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a fourth coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are not both 1;

setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and

setting a partial product p(i, k) to 1 when the multi-multiplication indication signal is 1, or setting a partial product p(i, k) to the second intermediate item when the multi-multiplication indication signal is 0.

12 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a fifth coder configured to perform coding operation comprising:

setting a partial product p(i, k) to the single-multiplication control signal SCi when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are 1; or

setting a partial product p(i, k) to an inversion of the single-multiplication control signal SCi when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are not both 1.

13 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a sixth coder configured to perform coding operation comprising:

setting a partial product p(i, k) to an inversion of the control signal Si when both the first selection signal M1Mi and the first bit b[k] in the second value are 1 or both the second selection signal M2Mi and the first bit b[k] in the second value are 1; or

setting a partial product p(i, k) to the control signal Si when the first selection signal M1Mi and the first bit b[k] in the second value are not both 1 and the second selection signal M2Mi and the first bit b[k] in the second value are not both 1.

14 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a seventh coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are not both 1;

setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and

setting a partial product p(i, k) to the second intermediate item when the single-multiplication indication signal is 1, or setting a partial product p(i, k) to 0 when the single-multiplication indication signal is 0.

15 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise an eighth coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the first bit b[k] in the second value are not both 1;

setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and

setting a partial product p(i, k) to the second intermediate item when the single-multiplication indication signal is 1, or setting a partial product p(i, k) to an inversion of the second intermediate item when the single-multiplication indication signal is 0.

16 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a ninth coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are 1 or both the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are 1, or setting a first intermediate item to 0 when the first single-multiplication selection signal SM1Mi and the first bit b[k] in the second value are not both 1 and the second single-multiplication selection signal SM2Mi and the second bit b[k−1] in the second value are not both 1;

setting a second intermediate item to an inversion of the single-multiplication control signal SCi when the first intermediate item is 1, or setting a second intermediate item to the single-multiplication control signal SCi when the first intermediate item is 0; and

setting a partial product p(i, k) to 1 when the first multi-multiplication control signal MCi is 1, or setting a partial product p(i, k) to the second intermediate item when the first multi-multiplication control signal MCi is 0.

17 . The multi-mode fusion multiplier according to claim 3 , wherein the Q groups of fusion coders further comprise a tenth coder configured to perform coding operations comprising:

setting a first intermediate item to 1 when both the multi-multiplication indication signal and the first bit b[k−1] in the second value are 1 or both the single-multiplication indication signal and the second bit b[k] in the second value are 1, or setting a first intermediate item to 0 when the multi-multiplication indication signal and the first bit b[k−1] in the second value are not both 1 and the single-multiplication indication signal and the second bit b[k] in the second value are not both 1;

setting a second intermediate item to 1 when both the first intermediate item and the first selection signal M1Mi are 1 or both the second selection signal M2Mi and the first bit b[k−1] are 1, or setting a second intermediate item to 0 when the first intermediate item and the first selection signal M1Mi are not both 1 and the second selection signal M2Mi and the first bit b[k−1] are not both 1;

setting a third intermediate item to an inversion of the second multi-multiplication control signal MCNi when the second intermediate item is 1, or setting a third intermediate item to the second multi-multiplication control signal MCNi when the second intermediate item is 0; and

setting a partial product p(i, k) to an inversion of the third intermediate item when the multi-multiplication indication signal is 1, or setting a partial product p(i, k) to the third intermediate item when the multi-multiplication indication signal is 0.

18 . A method performed by a multi-mode fusion multiplier comprising P precoders, Q groups of fusion coders, and a compressor, the method comprising:

receiving A[m 1 −1:0] and B[m 2 −1:0] as inputs to a binary single-multiplication operation A[m 1 −1:0]×B[m 2 −1:0] or an accumulated sum operation of 2N binary multiplications A0[m3−1:0]×B0[m 4 −1:0], wherein m 1 ≥2N×m 3 , m 2 ≥2N×m 4 , N is a positive integer, and m 1 , m 2 , m 3 , m 4 , P, and Q are integers greater than 1;

precoding, by the P precoders of the multi-mode fusion multiplier, a first value based on a single-multiplication indication signal or a multi-multiplication indication signal, to provide a precoding result, wherein the first value is A[m 1 −1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the first value comprises 2N pieces of A0[m 3 −1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of A0[m 3 −1:0] are arranged in a sequence from a low digit weight to a high digit weight;

coding, by the Q groups of fusion coders of the multi-mode fusion multiplier, the precoding result and a second value, to provide a plurality of partial products, wherein the second value is B[m 2 −1:0] when the single-multiplication indication signal indicates that the single-multiplication operation is performed, or the second value comprises 2N pieces of B0[m 4 −1:0] when the multi-multiplication indication signal indicates that the accumulated sum operation is performed, wherein the 2N pieces of B0[m 4 −1:0] are arranged in a sequence from a high digit weight to a low digit weight; and

compress, by the compressor, the plurality of partial products, to provide two accumulated values, wherein a sum of the two accumulated values is a result of the single-multiplication operation or the accumulated sum operation.