Data processing device
View Patent ↗A data processing device includes an instruction issue circuit configured to issue instructions; a plurality of execution circuits configured to execute, in parallel, the instructions issued from the instruction issue circuit; and a plurality of delay circuits configured to delay arrival timings of when the instructions issued from the instruction issue circuit arrive at the plurality of execution circuits, the plurality of delay circuits being arranged between the instruction issue circuit and the plurality of execution circuits. The arrival timings of the instructions arriving at at least two execution circuits included in the plurality of execution circuits are different from each other.
1 . A data processing device comprising:
an instruction issue circuit configured to issue an instruction that specifies at least a type of data operation;
a plurality of execution circuits, each configured to receive the instruction issued by the instruction issue circuit and to execute, in parallel, the data operation of the type specified by the instruction; and
a plurality of delay circuits configured to stagger respective arrival timings at which the instruction issued by the instruction issue circuit arrives at corresponding execution circuits of the plurality of execution circuits, by delaying the instruction that specifies the type of the data operation and that is issued by the instruction issue circuit, each of the plurality of delay circuits being arranged between the instruction issue circuit and a corresponding execution circuit of the plurality of execution circuits,
wherein the plurality of delay circuits are configured to delay the instruction that specifies the type of the data operation by respective delay amounts, the respective delay amounts being set in the plurality of delay circuits based on an evaluation of power supply noise of the data processing device during the data operation by the plurality of execution circuits.
2 . The data processing device as claimed in claim 1 , wherein a difference between delay amounts of the plurality of delay circuits is an integer multiple of one-half of a period of a waveform of power supply noise generated when the plurality of execution circuits simultaneously start operations.
3 . The data processing device as claimed in claim 2 , wherein a number of delay circuits among the plurality of delay circuits in which each of different values in the delay amounts is set is substantially identical.
4 . The data processing device as claimed in claim 1 , further comprising a delay amount hold circuit configured to hold delay amount information indicating delay amounts to be set in the plurality of delay circuits,
wherein the delay amounts respectively set in the plurality of delay circuits are set according to the delay amount information held by the delay amount hold circuit.
5 . The data processing device as claimed in claim 4 , wherein each of the plurality of delay circuits includes N flip-flops connected in series, and set, from among the N flip-flops, a number of flip-flops corresponding to the delay amount information held by the delay amount hold circuit to delay the instruction that specifies the type of the data operation, a rest of the N flip-flops being not used to delay the instruction.
6 . The data processing device as claimed in claim 4 ,
wherein each of the plurality of delay circuits includes a first-in first-out (FIFO) queue that is controlled by a write pointer and a read pointer and that is configured by a memory,
wherein the write pointer and the read pointer are updated in conjunction with each other every time an instruction among the instructions is stored in the FIFO queue, and
wherein each of the delay amounts of the plurality of delay circuits is set by a difference between a value of the write pointer and a value of the read pointer.
7 . The data processing device as claimed in claim 1 ,
wherein the plurality of execution circuits operate in synchronization with a clock having a first frequency, and
wherein a time difference of the respective arrival timings at which the instruction delayed by the plurality of delay circuits arrives at the corresponding execution circuits of the plurality of execution circuits is at least one period of the clock.
8 . The data processing device as claimed in claim 1 , wherein the instruction issue circuit issues, as the instruction that specifies the type of the data operation, an arithmetic instruction that specifies an arithmetic operation, and each of the plurality of execution circuits is an arithmetic circuit configured to execute, as the data operation of the type specified by the instruction, the arithmetic operation based on the arithmetic instruction.
9 . The data processing device as claimed in claim 1 , wherein the instruction issue circuit issues, as the instruction that specifies the type of the data operation, a data transfer instruction that specifies a data transfer, and each of the plurality of execution circuits is a data transfer execution circuit configured to execute, as the data operation of the type specified by the instruction, the data transfer based on the data transfer instruction.
10 . The data processing device as claimed in claim 1 , wherein the instruction issue circuit, the plurality of execution circuits, and the plurality of delay circuits are mounted in one semiconductor chip.
11 . The data processing device as claimed in claim 1 , wherein the instruction issue circuit and the plurality of execution circuits are mounted on different semiconductor chips.
12 . The data processing device as claimed in claim 1 , further comprising a plurality of boards, at least one semiconductor chip being mounted on each of the plurality of boards,
wherein the instruction issue circuit and the plurality of execution circuits are mounted on semiconductor chips of different boards among the plurality of boards.
13 . The data processing device as claimed in claim 1 , wherein the instruction issue circuit is configured to output the instruction to the plurality of delay circuits in parallel.
14 . The data processing device as claimed in claim 1 , wherein the instruction issued by the instruction issue circuit arrives at the plurality of execution circuits through the plurality of delay circuits, respectively.
15 . The data processing device as claimed in claim 1 , wherein the plurality of execution circuits and the plurality of delay circuits have one-to-one correspondence.
16 . The data processing device as claimed in claim 1 , wherein the plurality of execution circuits and the plurality of delay circuits have many-to-one correspondence.
17 . The data processing device as claimed in claim 1 , wherein a simultaneous start of execution of the instruction by the plurality of execution circuits is avoided by the staggering of the arrival timings.
18 . The data processing device as claimed in claim 1 , further comprising a plurality of register files connected to the plurality of execution circuits on a one-to-one basis, each of the plurality of register files being dedicated for use by a corresponding execution circuit among the plurality of execution circuits.
19 . The data processing device as claimed in claim 1 , wherein the instruction further specifies at least one of a source address of data or a destination address of data.
20 . The data processing device as claimed in claim 1 , wherein the evaluation of the power supply noise includes measuring a waveform corresponding to the power supply noise.
21 . The data processing device as claimed in claim 1 , wherein the delay amounts of the plurality of delay circuits are respectively set from among at least three delay amounts based on the evaluation.
22 . The data processing device as claimed in claim 1 , wherein the plurality of delay circuits are divided into at least three groups, delay amounts of delay circuits in a first group being same as a first delay amount, delay amounts of delay circuits in a second group being same as a second delay amount, delay amounts of delay circuits in a third group being same as a third delay amount, and the first delay amounts, the second delay amounts, and the third delay amounts being different from each other.
23 . The data processing device claimed in claim 1 , further comprising a branching path extending from the instruction issue circuit to the plurality of execution circuits, each of the plurality of delay circuits being arranged between a branching point and the corresponding execution circuit of the plurality of execution circuits in a corresponding branch.
24 . The data processing device claimed in claim 1 , wherein the data processing device is a single instruction multiple data (SIMD) type processor or a single instruction multiple threads (SIMT) type processor.
25 . The data processing device claimed in claim 1 , further comprising an instruction fetch circuit configured to fetch the instruction held in a memory or a cache, and transfer the fetched instruction to the instruction issue circuit, wherein the instruction issue circuit includes an instruction decoder configured to decode the fetched instruction transferred from the instruction fetch circuit.
26 . The data processing device claimed in claim 1 , wherein each of the plurality of delay circuits is configured to receive a clock signal whose frequency is related to that of an operation clock of the plurality of execution circuits, and delay the instruction based on the clock signal.
27 . The data processing device claimed in claim 1 , wherein each of the plurality of delay circuits is formed by an optical circuit.
28 . A data processing device comprising:
an instruction issue circuit configured to issue a first instruction that specifies at least a type of data operation;
a plurality of execution circuits, each configured to receive the first instruction issued by the instruction issue circuit and to execute, in parallel, the data operation of the type specified by the first instruction; and
a plurality of delay circuits, each configured to be arranged between the instruction issue circuit and a corresponding execution circuit of the plurality of execution circuits and to delay an arrival timing at which the first instruction that specifies the type of the data operation and that is issued by the instruction issue circuit arrives at the corresponding execution circuit of the plurality of execution circuits,
wherein the plurality of delay circuits are configured to prevent the plurality of execution circuits from starting simultaneously to execute the first instruction, by staggering respective arrival timings at which the first instruction issued by the instruction issue circuit arrives at corresponding execution circuits of the plurality of execution circuits, and
wherein the plurality of delay circuits are configured to delay the first instruction by respective delay amounts that are determined based on an evaluation of power supply noise of the data processing device during the data operation by the plurality of execution circuits.
29 . The data processing device as claimed in claim 28 , wherein at least two of the plurality of delay circuits are configured to have different delay amounts from each other in order to make arrival timings at which the first instruction arrives at corresponding execution circuits of the plurality of execution circuits different from each other.
30 . A method executed on a data processing device, comprising:
issuing, by an instruction issue circuit, an instruction that specifies at least a type of data operation to be executed by a plurality of execution circuits;
staggering, by a plurality of delay circuits each being arranged between the instruction issue circuit and a corresponding execution circuit of the plurality of execution circuits, respective arrival timings at which the instruction that specifies the type of the data operation and that is issued by the instruction issue circuit arrives at corresponding execution circuits of the plurality of execution circuits, wherein the plurality of delay circuits delay the instruction by respective delay amounts, the respective delay amounts being set in the plurality of delay circuits based on an evaluation of power supply noise of the data processing device during the data operation by the plurality of execution circuits; and
executing in parallel, by the plurality of execution circuits, the data operation of the type specified by the instruction.