IP Library › Granted Patent US 12670017
Granted Patent B2
US 12670017 · App. 17/955,143 · Granted Jun 30, 2026

Application programming interface to indicate performance of barrier instruction

Inventors: Ze Long (San Jose, CA); Kyrylo Perelygin (Broomfield, CO); Harold Carter Edwards (Campbell, CA); Gokul Ramaswamy Hirisave Chandra Shekhara (Bangalore, IN); Jaydeep Marathe (Kirkland, WA); Ronny Meir Krashinsky (Portola Valley, CA); Girish Bhaskarrao Bharambe (Pune, IN)
Assignee: NVIDIA Corporation
G06F9/4881G06F8/456G06F9/30072G06F9/5044G06F9/505G06F9/522G06F9/544G06F9/545
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Quick Facts
Patent No.
US 12670017
App. No.
17/955,143
Granted
Jun 30, 2026
Kind
B2
Abstract

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction.

Claims (39)

1 . One or more processors, comprising:

circuitry to, in response to a call to an application programming interface (API), indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction to prevent performance of one or more other instructions until performance of barrier instructions by threads of each of the two or more blocks of threads.

2 . The one or more processors of claim 1 , wherein the two or more blocks of threads are in a group of multiple groups of blocks of threads of a software kernel.

3 . The one or more processors of claim 1 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.

4 . The one or more processors of claim 1 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.

5 . The one or more processors of claim 1 , wherein the barrier instruction is in each thread within the two or more blocks of threads.

6 . The one or more processors of claim 1 , wherein the two or more blocks of threads are of a grid of blocks of threads, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.

7 . The one or more processors of claim 1 , wherein the barrier instruction is further to prevent performance of one or more instructions until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.

8 . The one or more processors of claim 1 , wherein, the circuitry is further to, in response to the API call, cause performance of the one or more threads to stop until a condition is satisfied.

9 . The one or more processors of claim 1 , wherein, the circuitry is further to, in response to the API call, cause performance of the one or more threads to stop until all threads within the two or more blocks have performed the barrier instruction.

10 . A computer-implemented method comprising:

in response to a call to an application programming interface (API), indicating whether one or more threads within two or more blocks of threads have performed a barrier instruction to prevent performance of one or more other instructions until performance of barrier instructions by threads of each of the two or more blocks of threads.

11 . The computer-implemented method of claim 10 , wherein the two or more blocks of threads are in a group of multiple groups of blocks of threads of a software kernel.

12 . The computer-implemented method of claim 10 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.

13 . The computer-implemented method of claim 10 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.

14 . The computer-implemented method of claim 10 , wherein the barrier instruction is in each thread within the two or more blocks of threads.

15 . The computer-implemented method of claim 10 , wherein the two or more blocks of threads are of a grid of blocks of threads, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.

16 . The computer-implemented method of claim 10 , wherein the barrier instruction is further to prevent performance of one or more instructions until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.

17 . The computer-implemented method of claim 10 , further comprising, in response to the call to the API, causing performance of the one or more threads to stop until a condition is satisfied.

18 . The computer-implemented method of claim 10 , wherein the API is further to cause performance of the one or more threads to stop until all threads within the two or more blocks have performed the barrier instruction.

19 . A computer system comprising:

one or more processors and at least one memory storing executable instructions that, when executed by the one or more processors, are to in response to a call to an application programming interface (API), indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction to prevent performance of one or more other instructions until performance of barrier instructions by at least one thread of each of the two or more blocks of threads.

20 . The computer system of claim 19 , wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.

21 . The computer system of claim 19 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.

22 . The computer system of claim 19 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.

23 . The computer system of claim 19 , wherein the barrier instruction is in each thread within the two or more blocks of threads.

24 . The computer system of claim 19 , wherein the two or more blocks of threads are of a grid of blocks of threads, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.

25 . The computer system of claim 19 , wherein the barrier instruction is further to prevent performance of one or more instructions until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.

26 . The computer system of claim 19 , wherein, the one or more processors are further to, in response to the API call, cause performance of the one or more threads to stop until a condition is satisfied.

27 . The computer system of claim 19 , wherein, the one or more processors are further to, in response to the API call, cause performance of the one or more threads to stop until all threads within the two or more blocks have performed the barrier instruction.

28 . A non-transitory machine-readable medium having stored thereon a set of instructions, that when performed by one or more processors, are to in response to a call to an application programming interface (API), indicate whether one or more threads within two or more blocks of threads have performed a barrier instruction to prevent performance of one or more other instructions until performance of barrier instructions by threads of each of the two or more blocks of threads.

29 . The non-transitory machine-readable medium of claim 28 , wherein the two or more bocks of threads are in a group of multiple groups of blocks of threads of a software kernel.

30 . The non-transitory machine-readable medium of claim 28 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads.

31 . The non-transitory machine-readable medium of claim 28 , wherein the two or more blocks of threads are in a partition of a partitioning of blocks of threads of a grid of blocks of threads, the partitioning comprising multiple partitions.

32 . The non-transitory machine-readable medium of claim 28 , wherein the barrier instruction is in each thread within the two or more blocks of threads.

33 . The non-transitory machine-readable medium of claim 28 , wherein the two or more blocks of threads are of a grid of blocks of threads, and wherein the grid of blocks of threads comprises at least one thread whose performance is not dependent on whether any threads of the two or more blocks of threads have performed the barrier instruction.

34 . The non-transitory machine-readable medium of claim 28 , wherein the barrier instruction is further to prevent performance of one or more instructions until a condition has been satisfied, the condition based, at least in part, on performance of the barrier instruction by each thread of the two or more blocks of threads.

35 . The non-transitory machine-readable medium of claim 28 , wherein, the one or more processors are further to, in response to the API call, cause performance of the one or more threads to stop until a condition is satisfied.

36 . The non-transitory machine-readable medium of claim 28 , wherein, the one or more processors are further to, in response to the API call, cause performance of the one or more threads to stop until all threads within the two or more blocks have performed the barrier instruction.