Memory system and method

1 . A memory system comprising:

a memory including a plurality of storage regions, each of the plurality of storage regions including a word line and a plurality of memory cells connected to the word line; and

a controller configured to:

execute a first operation on each of the plurality of storage regions, wherein

the first operation includes (i) acquiring first data by comparing a first determination voltage with a threshold voltage of each of the plurality of memory cells in a first storage region of the plurality of storage regions, the first data being a part of second data stored in the first storage region, the second data being a group of data of a plurality of bits and the first data being a group of first bits among the plurality of bits; (ii) calculating a first fail-bit count of the first data; and (iii) executing or skipping a second operation based on a comparison between the calculated first fail-bit count and a threshold value, wherein

the second operation includes (i) acquiring the second data by comparing a second determination voltage with the threshold voltage of each of the plurality of memory cells in the first storage region; (ii) calculating a second fail-bit count of the second data; and (iii) updating the second determination voltage based on the second fail-bit count, and

wherein the second operation is executed after the (ii) calculating a first fail-bit count of the first data.

2 . The memory system according to claim 1 , wherein the controller is configured to:

in the first operation,

execute the second operation based on the calculated first fail-bit count being greater than the threshold value; and

skip the second operation based on the calculated first fail-bit count being less than the threshold value.

3 . The memory system according to claim 1 , wherein

each of the plurality of memory cells is configured to store the data of the plurality of bits.

4 . The memory system according to claim 3 , wherein the second operation further includes reading a group of data of all bits except for the first bits among the plurality of bits based on comparison between a third determination voltage and the threshold voltage of each memory cell in the first storage region, and acquiring the second data from the first data and the read group.

5 . The memory system according to claim 1 , wherein

characteristic information is associated with each of the plurality of storage regions, and

the controller is configured to specify the threshold value based on the characteristic information associated with the first storage region in the first operation.

6 . The memory system according to claim 1 , further comprising:

an error correction circuit configured to change a setting of an error correction capability and to perform error correction coding on data to be written to the plurality of storage regions, wherein

the controller is configured to specify the threshold value based on the setting of the error correction capability applied to the error correction coding on the second data in the first operation.

7 . The memory system according to claim 1 , further comprising:

an error correction circuit configured to change a setting of an error correction capability and to perform error correction coding on data to be written to the plurality of storage regions, wherein

characteristic information is associated with each of the plurality of storage regions, and

the controller is configured to specify the threshold value based on the characteristic information associated with the first storage region and the setting of the error correction capability applied to the error correction coding on the second data in the first operation.

8 . The memory system according to claim 1 , wherein the controller is configured to execute an error correction on third data which is the first data or the second data, and calculate a fail-bit count of the third data based on comparison between the third data before the error correction and the third data after the error correction.

9 . A method of controlling a memory, the method comprising:

executing a first operation on each of a plurality of storage regions of a memory, wherein

each of the plurality of storage regions includes a word line and a plurality of memory cells connected to the word line,

the first operation includes (i) acquiring first data by comparing a first determination voltage with a threshold voltage of each of the plurality of memory cells in a first storage region of the plurality of storage regions, the first data being a part of second data stored in the first storage region; (ii) calculating a first fail-bit count of the first data, the second data being a group of data of a plurality of bits and the first data being a group of first bits among the plurality of bits; and (iii) executing or skipping a second operation based on a comparison between the calculated first fail-bit count and a threshold value, wherein

the second operation includes (i) acquiring the second data by comparing a second determination voltage and the threshold voltage of each of the plurality of memory cells in the first storage region, (ii) calculating a second fail-bit count of the second data, and (iii) updating the second determination voltage based on the second fail-bit count, and

wherein the second operation is executed after the (ii) calculating a first fail-bit count of the first data.

10 . The method according to claim 9 , further comprising:

in the first operation,

executing the second operation based on the calculated first fail-bit count being greater than the threshold value; and

skipping the second operation based on the calculated first fail-bit count being less than the threshold value.

11 . The method according to claim 9 , wherein

each of the plurality of memory cells is configured to store the data of the plurality of bits.

12 . The method according to claim 11 , wherein the second operation further includes reading a group of data of all bits except for the first bits among the plurality of bits based on comparison between a third determination voltage and the threshold voltage of each memory cell in the first storage region, and acquiring the second data from the first data and the read group.

13 . The method according to claim 9 , wherein characteristic information is associated with each of the plurality of storage regions, the method further comprises:

specifying the threshold value based on the characteristic information associated with the first storage region in the first operation.

14 . The method according to claim 9 , further comprising:

changing a setting of an error correction capability and performing error correction coding on data to be written to the plurality of storage regions, and

specifying the threshold value based on the setting of the error correction capability applied to the error correction coding on the second data in the first operation.

15 . The method according to claim 9 , wherein characteristic information is associated with each of the plurality of storage regions, and the method further comprising:

changing a setting of an error correction capability and performing error correction coding on data to be written to the plurality of storage regions, and

specifying the threshold value based on the characteristic information associated with the first storage region and the setting of the error correction capability applied to the error correction coding on the second data in the first operation.

16 . The method according to claim 9 , further comprises:

executing an error correction on third data which is the first data or the second data; and

calculating a fail-bit count of the third data based on comparison between the third data before the error correction and the third data after the error correction.

17 . A memory system comprising:

a memory including a plurality of storage regions, each of the plurality of storage regions including a word line and a plurality of memory cells connected to the word line; and

a controller configured to:

execute a first operation on each of the plurality of storage regions, wherein

the first operation includes (i) acquiring first by comparing a first determination voltage with a threshold voltage of each of the plurality of memory cells in a first storage region of the plurality of storage regions, the first data being a part of second data stored in the first storage region, the second data being a group of data of a plurality of bits and the first data being a group of first bits among the plurality of bits; (ii) calculating a first fail-bit count of the first data; and (iii) executing or skipping a second operation based on a comparison between the calculated first fail-bit count and a threshold voltage, wherein

the second operation includes (i) executing a read operation on the first storage region, and (ii) updating a second determination voltage based on data obtained through the read operation, and

wherein the second operation is executed after the (ii) calculating a first fail-bit count of the first data.

18 . The memory system according to claim 17 , wherein

the controller is configured to:

in the first operation,

execute the second operation based on the calculated first fail-bit count being greater than the threshold value; and

skip the second operation based on the calculated first fail-bit count being less than the threshold value.

19 . The memory system according to claim 17 , wherein

characteristic information is associated with each of the plurality of storage regions, and

the controller is configured to specify the threshold value based on the characteristic information associated with the first storage region in the first operation.

20 . The memory system according to claim 17 , further comprising:

an error correction circuit configured to change a setting of an error correction capability and to perform error correction coding on data to be written to the plurality of storage regions, wherein

the controller is configured to specify the threshold value based on the setting of the error correction capability applied to the error correction coding on the second data in the first operation.