Circuit element link training in a memory device
A memory system includes a memory controller and memory circuitry. The memory controller outputs a first training signal. The memory circuitry is coupled to the memory controller. The memory circuitry includes a memory device and multiplexing data buffer circuitry. The multiplexing data buffer circuitry is coupled to the memory device. The multiplexing data buffer circuitry includes first circuitry and second circuitry. The second circuitry is coupled to the memory device. The second circuitry receives the first training signal from memory controller comprising first training data associated with the first circuitry, writes the first training data to the memory device, and read the written first training data from the memory device, and outputs the written first training data to the memory controller. The memory controller is configured to determine equalization parameters for the first circuitry based on the written first training data.
1 . A memory circuitry comprising:
memory devices; and
multiplexing data buffer circuitry coupled to the memory devices, the multiplexing data buffer circuitry comprising:
input/output pins;
first circuitry coupled to a first input/output pin of the input/output pins; and
second circuitries, wherein the second circuitries are coupled to the memory devices and a first one the second circuitries is configured to:
receive, during a first period, a first signal comprising first training data associated with the first circuitry, write the first training data to a first memory device of the memory devices, and read the written first training data from the first memory device, wherein the written first training data is used to determine equalization parameters for the first circuitry and the first signal is received via the first input/output pin; and
receive, during a second period non-overlapping with the first period, a second signal comprising second training data and write the second training data to the first memory device, wherein the written second training data is used to determine equalization parameters for the first one of the second circuitries, the second signal is received via a second input/output pin of the input/output pins.
2 . The memory circuitry of claim 1 , wherein the first one of the second circuitries is further configured to read the written second training data from the first memory device.
3 . The memory circuitry of claim 1 , wherein the first circuitry comprises pass-through circuitry configured to receive the first signal and output the first signal to the first one of the second circuitries.
4 . The memory circuitry of claim 1 , wherein the multiplexing data buffer circuitry further comprises third circuitry external to the first circuitry and configured to receive the first signal and output the first signal to the first one of the second circuitries.
5 . The memory circuitry of claim 1 , wherein the first circuitry is cyclic redundancy check circuitry.
6 . The memory circuitry of claim 1 , wherein the first one of the second circuitries is one of selection circuitry and buffer circuitry.
7 . The memory circuitry of claim 1 , wherein the first circuitry and the second circuitries are disposed on a substrate.
8 . The memory circuitry of claim 1 , wherein a routing length between the first circuitry and the first one of the second circuitries is less than a routing length between the first circuitry and each other of the second circuitries.
9 . The memory circuitry of claim 1 , wherein the memory circuitry is packaged as a dual in-line memory module.
10 . A memory system comprising:
a memory controller configured to output a first training signal and a second training signal; and
memory circuitry coupled to the memory controller and comprising:
memory devices; and
multiplexing data buffer circuitry coupled to the memory devices, the multiplexing data buffer circuitry comprising:
input/output pins;
first circuitry coupled to a first input/output pin of the input/output pins; and
second circuitries, wherein the second circuitries are coupled to the memory devices and a first one of the second circuitries is configured to:
receive, during a first period and via the first input/output pin, the first training signal from the memory controller comprising first training data associated with the first circuitry, write the first training data to a first memory device of the memory devices, and read the written first training data from the first memory device;
output the written first training data to the memory controller;
receive, during a second period non-overlapping with the first period and via a second input/output pin of the input/output pins, a second signal comprising second training data and write the second training data to the first memory device; and
output the written second training data to the memory controller, wherein the memory controller is configured to determine first equalization parameters for the first circuitry based on the written first training data and second equalization parameters for the first one of the second circuitries based on the written second training data.
11 . The memory system of claim 10 , wherein the first one of the second circuitries is further configured read the written second training data from the first memory device.
12 . The memory system of claim 10 , wherein the first circuitry comprises pass-through circuitry configured to receive the first training signal and output the first training signal to the first one of the second circuitries.
13 . The memory system of claim 10 , wherein the multiplexing data buffer circuitry further comprises third circuitry external to the first circuitry and configured to receive the first training signal and output the first training signal to the first one of the second circuitries.
14 . The memory system of claim 10 , wherein the first circuitry is cyclic redundancy check circuitry.
15 . The memory system of claim 10 , wherein the first one of the second circuitries is one of selection circuitry and buffer circuitry.
16 . A method comprising:
receiving, during a first period and at first circuitry of multiplexing data buffer circuitry of memory circuitry, a first signal comprising first training data associated with second circuitry of the multiplexing data buffer circuitry, wherein the first signal is received via a first input/output pins of input/output pins of the multiplexing data buffer circuitry;
writing, via the first circuitry and during the first period, the first training data to a first memory device of memory devices of the memory circuitry;
reading, via the first circuitry and during the first period, the written first training data from the first memory device;
receiving, during a second period and at the first circuitry, a second signal comprising second training data associated with the first circuitry, wherein the second signal is received via a second input/output pin of the input/output pins, wherein the first period and the second period are non-overlapping;
writing, via the first circuitry and during the second period, the second training data to the first memory device; and
determining equalization parameters for the second circuitry from the written first training data and equalization parameters for the first circuitry from the written second training data.
17 . The method of claim 16 further comprising:
reading, via the first circuitry, the written second training data from the first memory device.
18 . The method of claim 16 , wherein at least one of the first signal is received by the first circuitry from the second circuitry via pass-through circuitry of the first circuitry and the first signal is received by the first circuitry from third circuitry external to the second circuitry.
19 . The method of claim 16 , wherein the first circuitry is cyclic redundancy check circuitry.
20 . The method of claim 16 , wherein the second circuitry is one of selection circuitry and buffer circuitry.