IP Library › Granted Patent US 12670065
Granted Patent B2
US 12670065 · App. 18/733,319 · Granted Jun 30, 2026

Adaptive parity techniques for a memory device

Inventors: Justin Eno (El Dorado Hills, CA); William A. Melton (Shingle Springs, CA); Sean S. Eilert (Penryn, CA)
Assignee: Micron Technology, Inc.
G06F11/1068G06F11/073G06F11/076G06F11/0772G06F11/1064G06F11/3037
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Quick Facts
Patent No.
US 12670065
App. No.
18/733,319
Granted
Jun 30, 2026
Kind
B2
Abstract

Methods, systems, and devices for adaptive parity techniques for a memory device are described. An apparatus, such as a memory device, may use one or more error correction code (ECC) schemes, an error cache, or both to support access operations. The memory device may receive a command from a host device to read or write data. If the error cache includes an entry for the data, the memory device may read or write the data using a first ECC scheme. If the error cache does not include an entry for the data, the memory device may read or write the data without using an ECC scheme or using a second ECC scheme different than the first ECC scheme.

Claims (67)

1 . A memory device, comprising:

one or more memory arrays;

a cache comprising a plurality of entries indicating addresses of the one or more memory arrays; and

one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:

receive a command to read data from the one or more memory arrays, the command indicating an address associated with the data;

determine, based at least in part on receiving the command, whether the cache includes an entry indicating the address;

read the data from the one or more memory arrays; and

perform one or more error control processes on the data based at least in part on determining whether the cache includes the entry.

2 . The memory device of claim 1 , wherein the one or more error control processes comprise a first error control process and a second error control process, and wherein the one or more controllers are further configured to cause the memory device to:

determine that the cache includes the entry associated with the address,

wherein performing the one or more error control processes comprises performing the first error control process based at least in part on determining that the cache includes the entry.

3 . The memory device of claim 2 , wherein, to perform the first error control process, the one or more controllers are further configured to cause the memory device to:

determine whether one or more errors are present in the data using a first set of parity bits stored in the cache or a second set of parity bits stored in the one or more memory arrays, or both.

4 . The memory device of claim 1 , wherein the one or more error control processes comprise a first error control process and a second error control process, and wherein the one or more controllers are further configured to cause the memory device to:

determine that the cache does not include the entry associated with the address,

wherein performing the one or more error control processes comprises performing the second error control process based at least in part on determining that the cache does not include the entry.

5 . The memory device of claim 4 , wherein, to perform the second error control process, the one or more controllers are further configured to cause the memory device to:

determine whether one or more errors are present in the data using a set of parity bits stored in the one or more memory arrays.

6 . The memory device of claim 1 , wherein the one or more error control processes comprise at least a first error control process and a second error control process, wherein the first error control process supports detecting or correcting up to a first quantity of errors in the data, and the second error control process supports detecting or correcting up to a second quantity of errors in the data, the second quantity less than the first quantity.

7 . The memory device of claim 1 , wherein the one or more controllers are further configured to cause the memory device to:

identify one or more errors in the data based at least in part on performing the one or more error control processes; and

correct the one or more errors based at least in part on performing the one or more error control processes.

8 . The memory device of claim 7 , wherein the one or more controllers are further configured to cause the memory device to:

store the entry associated with the address to the cache based at least in part on identifying the one or more errors in the data and determining that the cache does not include the entry.

9 . The memory device of claim 1 , wherein the one or more controllers are further configured to cause the memory device to:

determine that no errors are present in the data based at least in part on performing the one or more error control processes.

10 . The memory device of claim 9 , wherein the one or more controllers are further configured to cause the memory device to:

remove the entry associated with the address from the cache based at least in part on determining that no errors are present in the data and determining that the cache includes the entry.

11 . The memory device of claim 1 , wherein the one or more controllers are further configured to cause the memory device to:

output the data based at least in part on performing the one or more error control processes.

12 . A memory device, comprising:

one or more memory arrays;

a cache comprising a plurality of entries indicating addresses of the one or more memory arrays; and

one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:

receive a command to write data to the one or more memory arrays, the command indicating an address associated with the data;

determine, based at least in part on receiving the command, whether the cache includes an entry indicating the address;

perform one or more error control processes based at least in part on determining whether the cache includes the entry; and

write the data to the one or more memory arrays based at least in part on performing the one or more error control processes.

13 . The memory device of claim 12 , wherein the one or more error control processes comprise a first error control process and a second error control process, and wherein the one or more controllers are further configured to cause the memory device to:

determine that the cache includes the entry associated with the address,

wherein performing the one or more error control processes comprises performing the first error control process based at least in part on determining that the cache includes the entry.

14 . The memory device of claim 13 , wherein, to perform the first error control process, the one or more controllers are further configured to cause the memory device to:

generate a first set of parity bits and a second set of parity bits associated with the data;

store the first set of parity bits in the cache with the entry; and

store the second set of parity bits in the one or more memory arrays.

15 . The memory device of claim 12 , wherein the one or more error control processes comprise a first error control process and a second error control process, and wherein the one or more controllers are further configured to cause the memory device to:

determine that the cache does not include the entry associated with the address,

wherein performing the one or more error control processes comprises performing the second error control process based at least in part on determining that the cache does not include the entry.

16 . The memory device of claim 15 , wherein, to perform the second error control process, the one or more controllers are further configured to cause the memory device to:

generate a set of parity bits associated with the data; and

store the set of parity bits in the one or more memory arrays.

17 . A memory device, comprising:

one or more memory arrays configured to store data;

a cache comprising a plurality of entries associated with the data; and

one or more controllers coupled with the one or more memory arrays and the cache, and configured to cause the memory device to:

perform one or more error control processes using the cache;

identify no errors are present in first data read from the one or more memory arrays based at least in part on performing the one or more error control processes; and

remove, from the cache, one or more entries associated with the first data based at least in part on identifying no errors are present in the first data.

18 . The memory device of claim 17 , wherein, to remove the one or more entries, the one or more controllers are further configured to cause the memory device to:

remove, from the cache, one or more addresses associated with the first data based at least in part on identifying no errors are present in the first data.

19 . The memory device of claim 17 , wherein the one or more controllers are further configured to cause the memory device to:

read the first data from the one or more memory arrays,

wherein performing the one or more error control processes is based at least in part on reading the first data.

20 . The memory device of claim 17 , wherein the one or more controllers are further configured to cause the memory device to:

increment a count based at least in part on identifying no errors are present in the first data, wherein the count is associated with a quantity of times that no errors are identified in data from the one or more memory arrays based at least in part on performing the one or more error control processes; and

determine whether the count satisfies a threshold based at least in part on incrementing the count,

wherein removing the one or more entries is based at least in part on determining that the count satisfies the threshold.