Self-learning asymmetric bit-flipping decoder for memory devices
Systems and methods for improving performance of a memory device, which includes a bit-flipping (BF) decoder, are described. The disclosed embodiments improve the performance of the memory device by selecting parameters for the BF decoder that are optimized for current conditions of the memory device An example method includes performing a first number of decoding iterations on a received codeword, tracking the number of bit errors during the decoding, and determining, based thereon, an asymmetric ratio associated with the codeword. The method further includes determining, based on the asymmetric ratio and a checksum associated with the codeword, a current set of parameters for configuring the BF decoder, and performing a second number of decoding iterations on the codeword to generate data that was encoded. An example system includes the BF decoder and a memory controller that are configured to perform the above-described method.
1 . A method for improving a performance of a memory device, comprising:
determining a current set of noise statistics associated with a first sector of a non-volatile memory of the memory device;
determining, based on the current set of noise statistics, a current set of values for one or more characteristics of the first sector of the non-volatile memory;
inputting the current set of values for the one or more characteristics to a neural network;
using the neural network to determine, based on the current set of values, a current set of parameters for a bit-flipping (BF) decoder in the memory device;
providing a codeword from the first sector to the BF decoder; and
performing, subsequent to configuring the BF decoder with the current set of parameters, a decoding operation on the codeword, using a parity check matrix associated with an error-correcting code, to generate data that was encoded,
wherein the neural network is trained using multiple sets of parameters for the BF decoder, and wherein each of the multiple sets of parameters is associated with a set of noise statistics corresponding to one of multiple sets of values for the one or more characteristics of the non-volatile memory.
2 . The method of claim 1 , wherein the current set of parameters comprises a flipping threshold for at least one set of iterations or column zone associated with the parity check matrix.
3 . The method of claim 1 , wherein the one or more characteristics of the non-volatile memory comprise a cumulative number of program/erase (PE) cycles, a data retention metric, a number of read disturb errors, a read/write temperature, or a wordline (WL) index.
4 . The method of claim 1 , wherein the current set of parameters is determined by the neural network using a greedy optimization algorithm.
5 . The method of claim 1 , wherein the BF decoder is configured on a per-sector basis.
6 . The method of claim 1 , wherein a latency of the neural network for determining the current set of parameters based on the current set of values is less than a read latency of the non-volatile memory.
7 . The method of claim 6 , wherein the read latency is a minimum read latency or an average read latency of the non-volatile memory.
8 . The method of claim 1 , wherein the current set of parameters is available to the BF decoder prior to the BF decoder receiving the codeword from the first sector.
9 . The method of claim 1 , wherein a firmware or a system on chip (SoC) associated with the memory device is configured to initiate a determination of the current set of parameters, based on the current set of values for the one or more characteristics, by the neural network.
10 . A method for improving a performance of a memory device, comprising:
receiving, by an iterative bit-flipping (BF) decoder in the memory device, a codeword and a checksum associated with the codeword;
performing a first number of iterations of a decoding operation on the codeword;
determining, based on a number of bit errors during the first number of iterations, an asymmetric ratio associated with the codeword;
determining, based on the checksum and the asymmetric ratio, a current set of parameters for the iterative BF decoder;
performing, subsequent to configuring the iterative BF decoder with the current set of parameters, a second number of iterations of the decoding operation on the codeword to generate data that was encoded,
wherein a sum of the first number of iterations and the second number of iterations is less than or equal to a maximum number of iterations configured for the iterative BF decoder.
11 . The method of claim 10 , wherein determining the asymmetric ratio comprises:
generating, after the first number of iterations, a hard decision for the codeword;
determining, based on comparing the hard decision to the codeword received by the iterative BF decoder, a first number of errors that flipped a one-valued bit to a zero-valued bit and a second number of errors that flipped the zero-valued bit to the one-valued bit; and
determining the asymmetric ratio as a ratio between the first number of errors and the second number of errors.
12 . The method of claim 10 , wherein determining the current set of parameters is based on a look-up table that stores multiple sets of parameters.
13 . The method of claim 12 , comprising:
generating, based on the checksum and the asymmetric ratio, an index value; and
selecting, based on the index value, one of the multiple sets of parameters in the look-up table as the current set of parameters.
14 . The method of claim 10 , wherein the memory device comprises a non-volatile memory, wherein determining the current set of parameters is based on using a neural network trained using multiple sets of parameters for the iterative BF decoder, and wherein each of the multiple sets of parameters is associated with a corresponding checksum and a corresponding asymmetric ratio.
15 . The method of claim 14 , wherein a latency of the neural network for determining the current set of parameters is less than a read latency of the non-volatile memory.
16 . The method of claim 15 , wherein the read latency is a minimum read latency or an average read latency of the non-volatile memory.
17 . An apparatus for improving a performance of a memory device, comprising:
a bit-flipping (BF) decoder; and
a memory controller configured to:
determine a current set of noise statistics associated with a first sector of a non-volatile memory of the memory device,
determine, based on the current set of noise statistics, a current set of values for one or more characteristics of the first sector of the non-volatile memory,
input the current set of values to a neural network, and
use the neural network to determine, based on the current set of values, a current set of parameters for the BF decoder,
wherein the BF decoder, subsequent to being configured with the current set of parameters, is configured to:
receive a codeword from the first sector, and
perform a decoding operation on the codeword, using a parity check matrix associated with an error-correcting code, to generate data that was encoded, and
wherein the neural network is trained using multiple sets of parameters for the BF decoder, and wherein each of the multiple sets of parameters is associated with a set of noise statistics corresponding to one of multiple sets of values for the one or more characteristics of the non-volatile memory.
18 . The apparatus of claim 17 , wherein the current set of parameters comprises a flipping threshold for at least one set of iterations or column zone associated with the parity check matrix.
19 . The apparatus of claim 17 , wherein the one or more characteristics of the non-volatile memory comprise a cumulative number of program/erase (PE) cycles, a data retention metric, a number of read disturb errors, a read/write temperature, or a wordline (WL) index.
20 . The apparatus of claim 17 , wherein a latency of the neural network for determining the current set of parameters based on the current set of values is less than a read latency of the non-volatile memory.