Identifying wordlines susceptible to deeper erase conditions

1 . A method comprising:

identifying a block of a non-volatile memory device that is scheduled for an erase operation;

determining, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation,

wherein the deeper erase condition causes an erase threshold voltage of a cell, after the erase operation, to decrease below an erase verify voltage, and

wherein the data structure identifies wordlines that are susceptible to deeper erase conditions;

performing a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition; and

performing the erase operation on the block after performing the programming operation.

2 . The method of claim 1 , wherein determining whether the wordline is susceptible to the deeper erase condition comprises:

determining a classification of the wordline regarding a susceptibility to the deeper erase condition after determining that the wordline is susceptible to the deeper erase condition; and

determining the predetermined bit pattern based on the classification.

3 . The method of claim 1 , comprising:

identifying the block as a block that is scheduled for an erase operation prior to determining whether the wordline is susceptible to the deeper erase condition.

4 . The method of claim 1 , wherein the data structure identifies:

one or more first wordlines, that have been identified as being susceptible to deeper erase conditions, for a first range of program erase cycles, and

one or more second wordlines, that have been identified as being susceptible to deeper erase conditions, for a second range of program erase cycles.

5 . The method of claim 1 , wherein the machine learning model is included in a plurality of machine learning models associated with different program/erase cycles, and

wherein the method comprises:

determining a number of program/erase cycles of the block; and

selecting the machine learning model based on the number of program/erase cycles of the block.

6 . The method of claim 1 , wherein the data structure is generated using characterization data that identifies different threshold voltages associated with two overlapped charge states.

7 . The method of claim 1 , wherein the machine learning model is trained to determine, based on read operations performed on the wordline after the block has been programmed, a first distribution of threshold voltages for a first charge state of the wordline,

wherein the first distribution of threshold voltages for the first charge state is a distribution of threshold voltages of an upper tail, and

wherein determining whether the wordline of the block is susceptible to the deeper erase condition comprises determining whether the wordline of the block is susceptible to the deeper erase condition based on the first distribution of threshold voltages.

8 . The method of claim 1 , comprising:

performing read operations, on one or more other non-volatile memory devices, to obtain training data for the machine learning model.

9 . A system comprising:

a controller, of a non-volatile memory device, to:

identify a block of the non-volatile memory device that is scheduled for an erase operation;

determine, using a machine learning model or a data structure, that a wordline of the block is susceptible to a deeper erase condition before the erase operation,

wherein the deeper erase condition causes an erase threshold voltage of a cell, after the erase operation, to decrease below an erase verify voltage; and

program a predetermined bit pattern on the wordline based on determining that the wordline is susceptible to the deeper erase condition,

wherein the predetermined bit pattern is programmed prior to the erase operation being performed on the block.

10 . The system of claim 9 , wherein the controller is to:

perform the erase operation on the block after programming the predetermined bit pattern on the wordline.

11 . The system of claim 10 , wherein the machine learning model comprises a plurality of machine learning models, and

wherein the controller is to:

select the machine learning model, from the plurality of machine learning models, based on a number of program erase cycles of the one or more blocks.

12 . The system of claim 9 , wherein the controller is to:

determine that the data structure identifies the wordline; and

program a predetermined bit pattern on the wordline based on the data structure identifying the wordline.

13 . The system of claim 9 , wherein the data structure identifies different wordlines, that have been identified as being susceptible to deeper erase conditions, for different ranges of program erase cycles.

14 . The system of claim 9 , wherein the wordline is a wordline that is most susceptible to the deeper erase condition.

15 . The system of claim 9 , wherein, to determine that the wordline is susceptible to the deeper erase condition, the controller is further to:

determine a classification of the wordline regarding a susceptibility to the deeper erase condition; and

determine the predetermined bit pattern based on the classification.

16 . The system of claim 9 , wherein the controller is to:

identify the block as a block that is scheduled for an erase operation.

17 . A computer program product comprising:

one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, the program instructions comprising:

program instructions to determine that a wordline, of a block of a non-volatile memory device, is susceptible to a deeper erase condition,

wherein the deeper erase condition causes an erase threshold voltage of a cell, after an erase operation, to decrease below an erase verify voltage;

program instructions to program a predetermined bit pattern on the wordline based on determining that the wordline is susceptible to the deeper erase condition; and

program instructions to perform the erase operation on the block after programming the predetermined bit pattern on the wordline.

18 . The computer program product of claim 17 , wherein the wordline is a wordline that is most susceptible to the deeper erase condition.

19 . The computer program product of claim 17 , wherein the program instructions comprise:

program instructions to identify the block as a block that is scheduled for an erase operation.

20 . The computer program product of claim 17 , wherein the program instructions to program the predetermined bit pattern comprise:

program instructions to program the predetermined bit pattern to increase a threshold voltage of the wordline.