Application programming interface to invalidate information

1 . One or more processors, comprising: circuitry to, in response to an application programming interface (API) call, manage cache consistency of cache information between a first and second cache respectively including a first and second cache location respectively identified by a first and second identifier so that cache information stored at the second cache location of the second cache identified by the second identifier is to be migrated to the first cache location of the first cache identified by the first identifier and the API is to prevent subsequent instructions of the first cache from being performed that use the migrated cache information until the cache information stored at the second cache location of the second cache identified by the second identifier is invalidated.

2 . The one or more processors of claim 1 , wherein the first cache location is in a first cache, the second location is in a second cache, and the API is to cause information in a portion of the second cache to be invalidated based, at least in part, on the address provided to the API as input.

3 . The one or more processors of claim 1 , wherein the first cache location is in a first cache, the second cache location is in a second cache, and the API is to cause the information to be invalidated based, at least in part, on the address, an indication of a first path that includes the first cache, and an indication of a second path that includes the second cache, where the second path does not include the first cache.

4 . The one or more processors of claim 1 , wherein the second cache location includes a portion of a cache that corresponds to a range of addresses.

5 . The one or more processors of claim 1 , wherein the API is to cause the information to be invalidated based, at least in part, on an indication of a size of an object represented by the information and an indication that the information has been stored in the first cache location.

6 . The one or more processors of claim 1 , wherein the second cache location is in a first level cache, the first cache location is in a second level cache, and a storage path of the information in the second level cache includes a different first level cache.

7 . The one or more processors of claim 1 , wherein the API is to perform a memory ordering operation that prevents a subsequent operation from being performed until the information is invalidated based, at least in part, on the address provided to the API as input.

8 . A system, comprising: one or more processors to, in response to an application programming interface (API), manage consistency of cache information between a first and second cache respectively including a first and second cache location respectively identified by a first and second identifier so that cache information stored at the second cache location of the second cache identified by the second identifier is to be migrated to the first cache location of the first cache identified by the first identifier and the API is to prevent subsequent instructions of the first cache from being performed that use the migrated cache information until the cache information stored at the second cache location of the second cache identified by the second identifier is invalidated.

9 . The system of claim 8 , wherein the address is a memory address and the API is to cause the information to be invalidated in a portion of a cache based, at least in part, on the memory address.

10 . The system of claim 8 , wherein the first cache location is in a first cache of a graphics processing unit (GPU) and the second cache location is in a portion of a second cache of the GPU.

11 . The system of claim 8 , wherein the information to be invalidated includes a tensor map.

12 . The system of claim 8 , wherein the API is to perform an acquire operation that prevents a subsequent operation from being performed until the information is invalidated.

13 . The system of claim 8 , wherein the API is to cause the information to be invalidated based, at least in part, on the address provided to the API as input and a size of an object.

14 . A method, comprising:

identifying by a first and second identifier cache information between a first and second cache respectively including a first and second cache location respectively;

invalidating information at the second cache location of the second cache identified by the second identifier to be migrated to the first cache location of the first cache identified by the first identifier, via an API; and

preventing, via the API, subsequent instructions of the first cache from being performed that use the migrated cache information until the cache information stored at the second cache location of the second cache identified by the second identifier is invalidated.

15 . The method of claim 14 , wherein an address is a memory address in global memory of a graphics processing unit (GPU) provided as input to the API.

16 . The method of claim 14 , wherein invalidating information includes invalidating information corresponding to one or more memory addresses in a portion of a second cache in response to performance of one or more memory operations in a first cache.

17 . The method of claim 14 , wherein invalidating information includes invalidating information that corresponds to a tensor map stored in a portion of a cache.

18 . The method of claim 14 , wherein the second cache location is in a first level cache, the first cache location is in a second level cache, and a storage path of the information in the second level cache includes a different first level cache.

19 . The method of claim 14 , wherein the second cache location is in a portion of a cache that corresponds to a range of addresses.

20 . A non-transitory computer-readable medium having stored thereon a set of instructions, which if performed by one or more processors, cause the one or more processors to at least perform the method of claim 14 .