Address translation preloading into input-output memory managemen unit (IOMMU) from processor's registers

1 . A method for preloading address translation information comprising:

storing, by an input-output memory management unit (IOMMU), the address translation information in a register set of memory management input-output (MMIO) registers, the address translation information comprising a virtual address and a corresponding physical address, wherein storing the address translation information in the register set comprises setting the address translation information in the register set from information stored in registers of a processor; and

loading, by the IOMMU, the address translation information into cache memory of the IOMMU.

2 . The method of claim 1 , further comprising:

writing a table entry comprising the address translation information into an IOMMU page table in system memory.

3 . The method of claim 1 , further comprising:

performing a table walk for the address translation information of an IOMMU page table stored in system memory; and

setting the address translation information into the registers of the processor.

4 . The method of claim 1 , wherein loading the address translation information into the cache memory comprises loading the address translation information internally within the IOMMU.

5 . The method of claim 1 , further comprising:

setting an enable bit of the register set to a disabled state after loading the address translation information into the cache memory; and

wherein storing the address translation information in the register set of the IOMMU comprises:

setting a 4-tuple comprising the virtual address, the corresponding physical address, a process address space ID (PASID), and a device ID, and

setting the enable bit to an enabled state after setting the 4-tuple.

6 . The method of claim 1 , wherein the MMIO registers comprise a plurality of register sets arranged as a set array, wherein storing the address translation information comprises storing additional address translation information in the plurality of register sets.

7 . The method of claim 6 , wherein storing the address translation information further comprises sending the address translation information and the additional address translation information in parallel to the MMIO registers of the IOMMU.

8 . The method of claim 1 , further comprising:

receiving, by the IOMMU, the address translation information directly from the processor.

9 . The method of claim 2 , further comprising:

performing a table walk for the address translation information of the IOMMU page table stored in the system memory;

setting the address translation information into the registers of the processor;

setting an enable bit of the register set to a disabled state after loading the address translation information into the cache memory;

wherein storing the address translation information in the register set of the IOMMU comprises

setting a 4-tuple comprising the virtual address, the corresponding physical address, a process address space ID (PASID), and a device ID, and

setting the enable bit to an enabled state after setting the 4-tuple;

wherein the MMIO registers comprise a plurality of register sets arranged as a set array, wherein storing the address translation information comprises storing additional address translation information in the plurality of register sets; and

wherein storing the address translation information further comprises sending the address translation information and the additional address translation information in parallel to the MMIO registers of the IOMMU.

10 . An input-output memory management unit (IOMMU) comprising:

cache memory; and

memory management input/output (MMIO) registers comprising a register set, the MMIO registers being configured to store address translation information in the register set, the address translation information comprising a virtual address and a corresponding physical address, the IOMMU being configured to load the address translation information into the cache memory internally within the IOMMU, wherein the MMIO registers are further configured to store the address translation information in the register set by setting the address translation information in the register set from information stored in registers of a processor.

11 . The IOMMU of claim 10 ,

wherein the register set comprises an enable bit configured to be set to an enabled state after storing the address translation information in the register set, and

wherein the IOMMU is further configured to set the enable bit to a disabled state after loading the address translation information into the cache memory.

12 . The IOMMU of claim 10 , wherein the address translation information comprises a 4-tuple comprising the virtual address, the corresponding physical address, a process address space ID (PASID), and a device ID.

13 . The IOMMU of claim 12 ,

wherein the register set comprises an enable bit stored in a register together with the device ID, the enable bit being configured to be set to an enabled state after storing the address translation information in the register set, and

wherein the IOMMU is further configured to set the enable bit to a disabled state after loading the address translation information into the cache memory.

14 . The IOMMU of claim 10 , wherein the MMIO registers comprise a plurality of register sets arranged as a set array, wherein storing the address translation information comprises storing additional address translation information in the plurality of register sets.

15 . The IOMMU of claim 14 , wherein the MMIO registers are further configured to receive the address translation information and the additional address translation information in parallel from the processor.

16 . A computing system comprising:

system memory comprising an IOMMU page table;

an input-output memory management unit (IOMMU) comprising memory management input/output (MMIO) registers comprising a register set and cache memory, the IOMMU being configured to:

store address translation information in the register set of the MMIO registers, the address translation information comprising a virtual address and a corresponding physical address; and

load the address translation information into the cache memory; and

a processor configured to send the address translation information directly to the IOMMU, the IOMMU being further configured to store the address translation information in the register set by setting the address translation information in the register set from information stored in registers of the processor.

17 . The computing system of claim 16 ,

wherein the processor is configured to execute software configured to

write a table entry into the IOMMU page table from the information stored in the registers of the processor.

18 . The computing system of claim 16 ,

wherein the processor is configured to execute software configured to

instruct the processor to perform a table walk of the IOMMU page table for the address translation information, and

instruct the processor to set the address translation information into registers of the processor.

19 . The computing system of claim 16 , wherein the IOMMU further comprises:

a hardware circuit configured to load the address translation information into the cache memory internally within the IOMMU.

20 . The computing system of claim 16 ,

wherein the MMIO registers comprise a plurality of register sets arranged as a set array, and

wherein the processor is configured to execute software configured to send the address translation information and additional address translation information in parallel directly to the IOMMU.