Techniques for pre-fetching information using pattern detection

1 . A memory system, comprising:

one or more memory devices; and

processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:

receive a plurality of read commands and one or more hibernate commands;

detect a sequential pattern of logical addresses based at least in part on respective logical addresses indicated by the plurality of read commands, respective transfer lengths for the plurality of read commands, or both;

determine whether to pre-fetch, from the one or more memory devices, information indicating a logical-to-physical address mapping for a next logical address according to the sequential pattern based at least in part on comparing a threshold value for pre-fetching the information with a ratio, the ratio being of hibernate commands to sequential read commands in the plurality of read commands; and

execute a subsequent read command based at least in part on determining whether to pre-fetch the information.

2 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

pre-fetch the information prior to executing the subsequent read command based at least in part on the ratio satisfying the threshold value for pre-fetching the information; and

store the pre-fetched information in a cache, wherein, to execute the subsequent read command, the processing circuitry is configured to cause the memory system to:

retrieve data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the pre-fetched information stored in the cache.

3 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

refrain from pre-fetching the information prior to executing the subsequent read command based at least in part on the ratio failing to satisfy the threshold value for pre-fetching the information, wherein, to execute the subsequent read command, the processing circuitry is configured to cause the memory system to:

fetch the information based at least in part on executing the subsequent read command, the information comprising a table that defines the logical-to-physical address mapping; and

retrieve data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the fetched table.

4 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

execute a hibernate command of the one or more hibernate commands;

flush data from a cache into the one or more memory devices based at least in part on executing the hibernate command; and

enter a low power state based at least in part on executing the hibernate command.

5 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

increment a first count value for each sequential read command of the plurality of read commands; and

increment a second count value for each hibernate command of the one or more hibernate commands, wherein the processing circuitry is configured to cause the memory system to determine the ratio based at least in part on the second count value and the first count value.

6 . The memory system of claim 1 , wherein the threshold value for pre-fetching the information comprises a threshold ratio of 1:1.

7 . The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:

receive one or more second read commands after the plurality of read commands, the one or more second read commands indicating respective second logical addresses non-sequential to the respective logical addresses; and

reset, based at least in part on the respective second logical addresses being non-sequential to the respective logical addresses, a count value for pattern detection, a count value for each hibernate command, the ratio of hibernate commands to sequential read commands, or any combination thereof.

8 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of an electronic device, cause the electronic device to:

receive a plurality of read commands and one or more hibernate commands;

detect a sequential pattern of logical addresses based at least in part on respective logical addresses indicated by the plurality of read commands, respective transfer lengths for the plurality of read commands, or both;

determine whether to pre-fetch, from one or more memory devices, information indicating a logical-to-physical address mapping for a next logical address according to the sequential pattern based at least in part on comparing a threshold value for pre-fetching the information with a ratio, the ratio being of hibernate commands to sequential read commands in the plurality of read commands; and

execute a subsequent read command based at least in part on determining whether to pre-fetch the information.

9 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

pre-fetch the information prior to executing the subsequent read command based at least in part on the ratio satisfying the threshold value for pre-fetching the information; and

store the pre-fetched information in a cache, wherein, to execute the subsequent read command, the instructions further cause the electronic device to:

retrieve data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the pre-fetched information stored in the cache.

10 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

refrain from pre-fetching the information prior to executing the subsequent read command based at least in part on the ratio failing to satisfy the threshold value for pre-fetching the information, wherein, to execute the subsequent read command, the instructions further cause the electronic device to:

fetch the information based at least in part on executing the subsequent read command, wherein the information comprises a table that defines the logical-to-physical address mapping; and

retrieve data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the fetched table.

11 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

execute a hibernate command of the one or more hibernate commands;

flush data from a cache into the one or more memory devices based at least in part on executing the hibernate command; and

enter a low power state based at least in part on executing the hibernate command.

12 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

increment a first count value for each sequential read command of the plurality of read commands; and

increment a second count value for each hibernate command of the one or more hibernate commands, wherein the instructions further cause the electronic device to determine the ratio based at least in part on the second count value and the first count value.

13 . The non-transitory computer-readable medium of claim 8 , wherein the threshold value for pre-fetching the information comprises a threshold ratio of 1:1.

14 . The non-transitory computer-readable medium of claim 8 , wherein the instructions, when executed by the processing circuitry of the electronic device, further cause the electronic device to:

receive one or more second read commands after the plurality of read commands, the one or more second read commands indicating respective second logical addresses non-sequential to the respective logical addresses; and

reset, based at least in part on the respective second logical addresses being non-sequential to the respective logical addresses, a count value for pattern detection, a count value for each hibernate command, the ratio of hibernate commands to sequential read commands, or any combination thereof.

15 . A method by a memory system, comprising:

receiving a plurality of read commands and one or more hibernate commands;

detecting a sequential pattern of logical addresses based at least in part on respective logical addresses indicated by the plurality of read commands, respective transfer lengths for the plurality of read commands, or both;

determining whether to pre-fetch, from one or more memory devices, information indicating a logical-to-physical address mapping for a next logical address according to the sequential pattern based at least in part on comparing a threshold value for pre-fetching the information with a ratio, the ratio being of hibernate commands to sequential read commands in the plurality of read commands; and

executing a subsequent read command based at least in part on determining whether to pre-fetch the information.

16 . The method of claim 15 , further comprising:

pre-fetching the information prior to executing the subsequent read command based at least in part on the ratio satisfying the threshold value for pre-fetching the information; and

storing the pre-fetched information in a cache, wherein executing the subsequent read command comprises:

retrieving data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the pre-fetched information stored in the cache.

17 . The method of claim 15 , further comprising:

refraining from pre-fetching the information prior to executing the subsequent read command based at least in part on the ratio failing to satisfy the threshold value for pre-fetching the information, wherein executing the subsequent read command comprises:

fetching the information based at least in part on executing the subsequent read command, wherein the information comprises a table that defines the logical-to-physical address mapping; and

retrieving data from the one or more memory devices for the executed subsequent read command based at least in part on the logical-to-physical address mapping defined by the fetched table.

18 . The method of claim 15 , further comprising:

executing a hibernate command of the one or more hibernate commands;

flushing data from a cache into the one or more memory devices based at least in part on executing the hibernate command; and

entering a low power state based at least in part on executing the hibernate command.

19 . The method of claim 15 , further comprising:

incrementing a first count value for each sequential read command of the plurality of read commands; and

incrementing a second count value for each hibernate command of the one or more hibernate commands, wherein the memory system determines the ratio based at least in part on the second count value and the first count value.

20 . The method of claim 15 , wherein the threshold value for pre-fetching the information comprises a threshold ratio of 1:1.