Input/output (I/O) register reflected in CPU memory

1 . A method comprising:

configuring, by a host processor, a queue for an input/output (I/O) controller, the queue located in a memory of the I/O controller;

specifying, by the host processor, a memory address for updates by the I/O controller, the memory address located in a main memory connected to the host processor;

submitting, by the host processor, an entry in the queue for a command to be executed by the I/O controller; and

reading, by the host processor, the memory address, instead of a hardware register located in the I/O controller, to determine that the command has been executed by the I/O controller, wherein the I/O controller is configured to, in response to executing the command, write contents of the hardware register into the memory address.

2 . The method of claim 1 , further comprising:

updating, by the host processor, a tail index for the queue upon submitting the entry in the queue.

3 . The method of claim 2 , further comprising:

writing, by the host processor, the updated tail index for the queue in a doorbell register.

4 . The method of claim 3 , wherein the doorbell register is located in the I/O controller.

5 . The method of claim 1 , wherein the queue is a submission queue, and wherein the method further comprises:

configuring, by the host processor, a completion queue for the I/O controller, the completion queue located in the memory of the I/O controller.

6 . The method of claim 5 , wherein the submission queue and the completion queue are circular buffers in a same ring.

7 . The method of claim 5 , wherein the submission queue and the completion queue are mapped in an address space of the host processor.

8 . A system comprising:

a host processor;

a main memory connected to the host processor; and

an input/output (I/O) controller coupled to the host processor via an I/O bus, the I/O controller having a memory;

wherein the host processor is configured to execute instructions to:

configure a queue for the I/O controller, the queue located in the memory of the I/O controller;

specify a memory address for updates by the I/O controller, the memory address located in the main memory;

submit an entry in the queue for a command to be executed by the I/O controller; and

read the memory address, instead of a hardware register located in the I/O controller, to determine that the command has been executed by the I/O controller, wherein the I/O controller is configured to, in response to executing the command, write contents of the hardware register into the memory address.

9 . The system of claim 8 , wherein the host processor is further configured to:

update a tail index for the queue upon submitting the entry in the queue.

10 . The system of claim 9 , wherein the host processor is further configured to:

write the updated tail index for the queue in a doorbell register.

11 . The system of claim 10 , wherein the doorbell register is located in the I/O controller.

12 . The system of claim 8 , wherein the queue is a submission queue, and wherein the host processor is further configured to:

configure a completion queue for the I/O controller, the completion queue located in the memory of the I/O controller.

13 . The system of claim 12 , wherein the submission queue and the completion queue are circular buffers in a same ring.

14 . The system of claim 12 , wherein the submission queue and the completion queue are mapped in an address space of the host processor.

15 . A non-transitory computer-readable medium comprising instructions that, when executed by a host processor, cause the host processor to perform operations comprising:

configuring, by the host processor, a queue for an input/output (I/O) controller, the queue located in a memory of the I/O controller;

specifying, by the host processor, a memory address for updates by the I/O controller, the memory address located in a main memory connected to the host processor;

submitting, by the host processor, an entry in the queue for a command to be executed by the I/O controller; and

reading, by the host processor, the memory address, instead of a hardware register located in the I/O controller, to determine that the command has been executed by the I/O controller, wherein the I/O controller is configured to, in response to executing the command, write contents of the hardware register into the memory address.

16 . The non-transitory computer-readable medium of claim 15 , wherein the operations further comprise:

updating, by the host processor, a tail index for the queue upon submitting the entry in the queue.

17 . The non-transitory computer-readable medium of claim 16 , wherein the operations further comprise:

writing, by the host processor, the updated tail index for the queue in a doorbell register.

18 . The non-transitory computer-readable medium of claim 17 , wherein the doorbell register is located in the I/O controller.

19 . The non-transitory computer-readable medium of claim 15 , wherein the queue is a submission queue, and wherein the operations further comprise:

configuring, by the host processor, a completion queue for the I/O controller, the completion queue located in the memory of the I/O controller.

20 . The non-transitory computer-readable medium of claim 19 , wherein the submission queue and the completion queue are circular buffers in a same ring, and wherein the submission queue and the completion queue are mapped in an address space of the host processor.