Clock domain transfer interface for high bandwidth data transfer using event transfer blocks

Inventors: Eric Wayne Mahurin (Austin, TX); Hitesh Kumar Gupta (Sunnyvale, CA); Francisco Perez (San Diego, CA)

Assignee: QUALCOMM Incorporated

G06F13/1689 G06F13/1673

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Quick Facts

Patent No.: US 12670110
App. No.: 18/601,341
Granted: Jun 30, 2026
Kind: B2

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Abstract

A clock domain crossing interface is described. The clock domain crossing interface includes a transmit clock domain and a receive clock domain using a different clock from the transmit clock domain. The clock domain crossing interface also includes a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain. The FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain. The clock domain crossing interface further includes a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain. The clock domain crossing interface also includes a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain.

Claims (35)

1 . A clock domain crossing interface, comprising:

a transmit clock domain;

a receive clock domain using a different clock from the transmit clock domain;

a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain, in which the FIFO buffer to store ordered transactions sent from the transmit clock domain to the receive clock domain;

a transmit clock domain event transfer block to notify the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain;

a receive clock domain event transfer block to notify the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain;

a transmit clock domain synchronizer to decouple a read pointer in the receive clock domain from a gray read count maintained by the transmit clock domain synchronizer; and

a receive clock domain synchronizer to decouple a write pointer in the transmit clock domain from a gray write count maintained by the receive clock domain synchronizer.

2 . The clock domain crossing interface of claim 1 ,

in which the FIFO buffer is coupled between the transmit domain synchronizer and the receive domain synchronizer.

3 . The clock domain crossing interface of claim 1 , further comprising a read/write logic to provide a vacancy/occupancy-based read/write control of the FIFO buffer.

4 . The clock domain crossing interface of claim 1 , further comprises a power domain crossing interface.

5 . The clock domain crossing interface of claim 2 , in which the transmit domain synchronizer is used to exchange the gray read count between the receive clock domain and the transmit clock domain, and in which the receive domain synchronizer is used to exchange the gray write count between the transmit clock domain and the receive clock domain.

6 . The clock domain crossing interface of claim 3 , in which the read/write logic comprises a binary vacancy count block to control a write to the FIFO buffer according to the gray read count from the receive clock domain event transfer block.

7 . The clock domain crossing interface of claim 3 , in which the read/write logic comprises a binary occupancy count block to control a read of the FIFO buffer according to the gray write count from the transmit clock domain event transfer block.

8 . The clock domain crossing interface of claim 3 , in which the read/write logic comprises a binary vacancy count block to control a write to the FIFO buffer according to a vacancy in the FIFO buffer to push the write onto the FIFO buffer in response to a received pull event from the receive clock domain event transfer block.

9 . The clock domain crossing interface of claim 3 , in which the read/write logic comprises a binary occupancy count block to control a read of the FIFO buffer according to an occupancy in the FIFO buffer to pull the read from the FIFO buffer in response to a received push event from the transmit clock domain event transfer block.

10 . A processor-implemented method for a clock domain crossing interface, the processor-implemented method comprising:

storing ordered transactions sent from a transmit clock domain to a receive clock domain in a first-in-first-out (FIFO) buffer coupled between the transmit clock domain and the receive clock domain;

notifying the receive clock domain of a new transaction pushed onto the FIFO buffer in the transmit clock domain;

notifying the transmit clock domain of a new transaction pulled from the FIFO buffer in the receive clock domain;

decoupling a read pointer in the receive clock domain from a gray read count maintained by a transmit clock domain synchronizer; and

decoupling a write pointer in the transmit clock domain from a gray write count maintained by a receive clock domain synchronizer to enable an odd number of entries in the FIFO buffer.

11 . The processor-implemented method of claim 10 , further comprising:

exchanging, using the transmit clock domain synchronizer, the gray read count between the receive clock domain and the transmit clock domain;

exchanging, using the receive clock domain synchronizer, the gray write count between the transmit clock domain and the receive clock domain; and

providing, using read/write logic, a vacancy/occupancy-based read/write control of the FIFO buffer, coupled between the transmit clock domain synchronizer and the receive clock domain synchronizer.

12 . The processor-implemented method of claim 11 , further comprising sending, by the transmit clock domain synchronizer, a push transaction event onto the FIFO buffer to the receive clock domain.

13 . The processor-implemented method of claim 11 , further comprising sending, by the receive clock domain synchronizer, a pull transaction event from the FIFO buffer to the transmit clock domain.

14 . The processor-implemented method of claim 11 , further comprising prohibiting a push of the new transaction onto the FIFO buffer when a vacancy count is zero.

15 . The processor-implemented method of claim 11 , further comprising prohibiting a pull of the new transaction from the FIFO buffer when an occupancy count is zero.

16 . The processor-implemented method of claim 11 , further comprising maintaining the read pointer in the receive clock domain as a function of a number of pulls from the FIFO buffer.

17 . The processor-implemented method of claim 11 , further comprising maintaining the write pointer in the transmit clock domain as a function of a number of pushes onto the FIFO buffer.

18 . The processor-implemented method of claim 12 , further comprising incrementing an occupancy count in a binary occupancy count block in the receive clock domain in response to the push transaction event onto the FIFO buffer from the transmit clock domain synchronizer.

19 . The processor-implemented method of claim 13 , further comprising incrementing a vacancy count in a binary vacancy count block in the transmit clock domain in response to the pull transaction event from the FIFO buffer from the receive clock domain synchronizer.