Semiconductor apparatus and semiconductor system

1 . A semiconductor system comprising:

a semiconductor apparatus including a plurality of memories;

a controller to control the semiconductor apparatus;

a command address bus through which control signals that are used for the controller to control the semiconductor apparatus are transmitted and received; and

a baseboard management controller configured to assign an identifier (ID) to each of the plurality of memories, in order to perform training operations that train the control signals,

wherein the semiconductor apparatus further comprises a buffer configured to transmit, to each of the plurality of memories, the control signals that are received through the command address bus from the controller,

wherein the ID assigned by the baseboard management controller corresponds to a location at which each of the plurality of memories is disposed or a distance between each of the plurality of memories and the buffer.

2 . The semiconductor system of claim 1 , wherein each of the plurality of memories compares the assigned ID with a preset ID, and performs an on-die termination (ODT) setting operation based on results of the comparison between the assigned ID and the preset ID, among the training operations.

3 . The semiconductor system of claim 2 , wherein the preset ID comprises an ID that is assigned to memories disposed at an outermost of the semiconductor apparatus or an ID that is assigned to memories at a longest distance from the buffer.

4 . The semiconductor system of claim 3 , wherein each of the plurality of memories

stores a first ODT setting value and a second ODT setting value,

performs the ODT setting operation based on the first ODT setting value when it is determined that the assigned ID is the same as the preset ID, and

performs the ODT setting operation based on the second ODT setting value when it is determined that the assigned ID is different from the preset ID.

5 . A semiconductor apparatus comprising:

a plurality of memories; and

a buffer configured to transmit, to each of the plurality of memories, control signals for controlling the plurality of memories, through a command address bus,

wherein each of the plurality of memories is configured to receive an identifier (ID) that is assigned by a baseboard management controller through a management bus in order to train the control signals that are transmitted through the command address bus,

wherein the ID assigned by the baseboard management controller corresponds to a location at which each of the plurality of memories is disposed or a distance between each of the plurality of memories and the buffer.

6 . The semiconductor apparatus of claim 5 , wherein each of the plurality of memories comprises:

a comparator configured to compare the assigned ID with a preset ID;

a mode register set configured to store a plurality of on-die termination (ODT) setting values; and

a selector configured to select one of the plurality of ODT setting values based on results of the comparison of the comparator.

7 . The semiconductor apparatus of claim 6 , wherein each of the plurality of memories performs an ODT setting operation based on the ODT setting value selected by the selector.

8 . The semiconductor apparatus of claim 6 , wherein the comparator compares whether the assigned ID is the same as the preset ID.

9 . A semiconductor system comprising:

a semiconductor apparatus;

a controller configured to control the semiconductor apparatus through a command address bus and a data bus; and

a baseboard management controller configured to control the semiconductor apparatus through a management bus,

wherein the semiconductor apparatus is configured to store data under a control of the controller, configured to output data stored in the semiconductor apparatus, and configured to perform an on-die termination (ODT) setting operation based on an identifier (ID) that is assigned by the baseboard management controller.

10 . The semiconductor system of claim 9 , wherein the semiconductor apparatus comprises a plurality of memories, and a buffer configured to transmit, to each of the plurality of memories, control signals that are received through the command address bus from the controller.

11 . The semiconductor system of claim 10 , wherein the assigned ID corresponds to a location at which each of the plurality of memories is disposed or a distance between each of the plurality of memories and the buffer.

12 . The semiconductor system of claim 11 , wherein each of the plurality of memories compares the ID assigned by the baseboard management controller and a preset ID, and performs the ODT setting operation based on results of the comparison.

13 . The semiconductor system of claim 12 , wherein the preset ID comprises an ID that is assigned to memories disposed at an outermost of the semiconductor apparatus or an ID that is assigned to memories at a longest distance from the buffer.

14 . The semiconductor system of claim 13 , wherein each of the plurality of memories

stores an ODT setting value when it is determined that the assigned ID is the same as the preset ID and an ODT setting value when it is determined that the assigned ID is different from the preset ID, and

selects one of the stored ODT setting values based on the results of the comparison between the assigned ID and the preset ID and performs the ODT setting operation.

15 . A semiconductor system comprising:

a semiconductor apparatus including a plurality of memories and a buffer;

a controller to control the semiconductor apparatus; and

a baseboard management controller configured to assign an identifier (ID) to each of the plurality of memories,

wherein the semiconductor apparatus is configured to perform an on-die termination (ODT) setting operation based on the assigned ID, and

wherein the assigned ID for each memory varies based on a distance between each memory and the buffer.