IP Library Granted Patent US 12670114
Granted Patent B2
US 12670114 · App. 18/400,192 · Granted Jun 30, 2026

Cable for routing signals in a system lacking a backplane

Inventors: P. Daniel Kangas (Raleigh, NC); Jean J. Xu (Cary, NC); Alan L. Painter (Apex, NC); James Michael Dupuy (Cary, NC)
Assignee: Lenovo (Singapore) Pte. Ltd.
G06F13/4068G06F13/4221G06F2213/0016G06F2213/0026
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Quick Facts
Patent No.
US 12670114
App. No.
18/400,192
Granted
Jun 30, 2026
Kind
B2
Abstract

An apparatus, system, and method for signal routing in a system lacking a backplane. One apparatus includes an interface card and a cable having a first connector configured to couple with a storage drive via the interface card, a second connector configured to couple with a motherboard, and a third connector configured to couple with a storage controller located apart from the motherboard. The cable routes control signals and data signals between the storage drive, the storage controller, and the motherboard.

Claims (51)

1 . An apparatus, comprising:

an interface card; and

a three-way cable providing a three-way hot-swappable connection between a storage drive, a motherboard, and a storage controller, the three-way cable comprising:

a first connector configured to couple the storage drive and the interface card;

a second connector configured to couple to the motherboard; and

a third connector configured to couple to the storage controller,

wherein:

the storage drive, the motherboard, and the storage controller are separate from and located apart from each other,

the three-way cable is separate from and detachably coupleable to the storage drive, the motherboard, and the storage controller to form the three-way hot-swappable connection between the storage drive, the motherboard, and the storage controller, and

the three-way cable routes control signals and data signals between the storage drive, the storage controller, and the motherboard.

2 . The apparatus of claim 1 , wherein the first connector comprises an Enterprise and Data Center Standard Form Factor (“EDSFF”) socket connector configured to receive an EDSFF edge connector.

3 . The apparatus of claim 1 , wherein the cable supports an eight data lane (“×8”) Peripheral Component Interconnect Express (“PCIe”) connection between the storage drive and the storage controller.

4 . The apparatus of claim 1 , wherein the interface card is configured to loop-back a Universal Backplane Management (“UBM”) signal to the motherboard, wherein the cable supports a UBM bus between the storage controller and a storage backplane controller located on the motherboard.

5 . The apparatus of claim 1 , wherein the interface card is configured to combine a first PCI Express Reset (“PERST”) signal received from the storage controller with a second PERST signal received from the motherboard, and wherein the interface card is further configured to output the combined signal to the storage drive.

6 . A system, comprising:

a motherboard;

a storage controller;

a storage bay lacking a backplane card;

a storage drive located in the storage bay; and

a three-way cable providing a three-way hot-swappable connection between the storage drive, the motherboard, and the storage controller, the three-way cable comprising:

a first connector configured to couple to the storage drive;

a second connector configured to couple to the motherboard; and

a third connector configured to couple to the storage controller,

wherein:

the storage drive, the motherboard, and the storage controller are separate from and located apart from each other,

the three-way cable is separate from and detachably coupleable to the storage drive, the motherboard, and the storage controller to form the three-way hot-swappable connection between the storage drive, the motherboard, and the storage controller, and

the three-way cable routes control signals and data signals between the storage drive, the storage controller, and the motherboard.

7 . The system of claim 6 , wherein the motherboard comprises power pins, ground pins, and hot-swap circuitry for the storage drive.

8 . The system of claim 6 , wherein the motherboard comprises at least one activity indicator, and wherein the cable routes one or more activity signals between the storage drive and the motherboard.

9 . The system of claim 6 , wherein the first connector comprises an Enterprise and Data Center Standard Form Factor (“EDSFF”) socket connector configured to receive an EDSFF edge connector.

10 . The system of claim 9 , further comprising a connector card coupled with the EDSFF socket connector and configured to adapt a non-EDSFF edge connector of the storage drive to the EDSFF socket connector.

11 . The system of claim 6 , wherein the cable supports an eight data lane (“×8”) Peripheral Component Interconnect Express (“PCIe”) connection between the storage drive and the storage controller.

12 . The system of claim 6 , wherein the cable further comprises an interface card configured to loop-back a Universal Backplane Management (“UBM”) signal to the motherboard.

13 . The system of claim 12 , wherein the cable supports a UBM bus between the storage controller and a storage backplane controller located on the motherboard.

14 . The system of claim 6 , wherein the cable further comprises an interface card configured to combine a first PCI Express Reset (“PERST”) signal received from the storage controller with a second PERST signal received from the motherboard, and wherein the interface card is configured to output the combined signal to the storage drive.

15 . The system of claim 6 , wherein the first connector is configured to support two storage drives.

16 . A method performed at a storage bay lacking a backplane, the method comprising:

detachably coupling a storage drive located in the storage bay to a first connector of a three-way cable;

detachably coupling a motherboard to a second connector of the three-way cable;

detachably coupling a storage controller located apart from the motherboard to a third connector of the three-way cable;

routing control signals and data signals between the storage drive, the storage controller, and the motherboard; and

routing one or more Inter-Integrated Circuit (“I2C”) sideband signals between the storage drive and at least one service processor located on the motherboard,

wherein:

the storage drive, the motherboard, and the storage controller are separate from and located apart from each other, and

the three-way cable is separate from and is detachably coupleable to the storage drive, the motherboard, and the storage controller to form a three-way hot-swappable connection between the storage drive, the motherboard, and the storage controller.

17 . The method of claim 16 , further comprising providing a Universal Backplane Management (“UBM”) bus between the storage controller and a storage backplane controller located on the motherboard, and looping-back a UBM signal from the storage controller to the motherboard.

18 . The method of claim 16 , further comprising:

combining a first PCI Express Reset (“PERST”) signal received from the storage controller with a second PERST signal received from the motherboard; and

outputting the combined signal to the storage drive.

19 . The apparatus of claim 1 , wherein the cable routes one or more Inter-Integrated Circuit (“I2C”) sideband signals between the storage drive and at least one service processor located on the motherboard.

20 . The system of claim 6 , wherein the cable routes one or more Inter-Integrated Circuit (“I2C”) sideband signals between the storage drive and at least one service processor located on the motherboard.