Testability circuitry placement within an integrated circuit design

1 . A method comprising:

partitioning, by a processor, a portion of an integrated circuit (IC) design that comprises Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry, into two or more sub-blocks based on a number of scan chains within the IC design;

assigning, by the processor, the scan chains to each of the two or more sub-blocks based on locations of end points within each of the scan chains; and

generating a layout of the IC design by placing the two or more sub-blocks of the partitioned DFT CODEC circuitry within the IC design based on the locations of end points within the scan chains and the assigned scan chains.

2 . The method of claim 1 , further comprising clustering the scan chains based on the locations of the end points, wherein the assigning comprises assigning the scan chains to each of the two or more sub-blocks based on the clustering.

3 . The method of claim 1 , wherein the clustering comprises clustering the scan chains based on a type, and wherein the assigning comprises assigning the scan chains to each of the two or more sub-blocks based on the clustering.

4 . The method of claim 1 , wherein the partitioning the DFT CODEC circuitry comprises determining that each of the two or more sub-blocks are associated with a threshold number of scan chains.

5 . The method of claim 1 , wherein the assigning the scan chains to each of the two or more sub-blocks comprises generating a mapping between the end points and the two or more sub-blocks.

6 . The method of claim 1 , further comprising tuning multiplexer partitioning based on annotated metadata, wherein the annotated metadata comprises one or more of:

a number of the two or more sub-blocks;

the locations of end points within the scan chains, and

the assigned scan chains to each of the two or more sub-blocks.

7 . The method of claim 1 , wherein the generating the layout of the IC design by placing the DFT CODEC further comprises conducting netweight modeling to determine an acceptable level of pull while maintaining a desired spread of the two or more sub-blocks on the IC design.

8 . The method of claim 1 , wherein the partitioning comprises partitioning the DFT CODEC circuitry into four, eight, or sixteen pairs of compressor-decompressor sub-blocks.

9 . The method of claim 1 , wherein the two or more sub-blocks are for decompressor circuitry of the DFT CODEC circuitry.

10 . A system, comprising:

a processor; and

memory storing instructions that, when executed by the processor

cause the processor to:

partition a portion of an integrated circuit (IC) design that comprises Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry, into two or more sub-blocks based on a number of scan chains within the IC design;

assign the scan chains to each of the two or more sub-blocks based on locations of end points within each of the scan chains; and

generate a layout of the IC design by placing the two or more sub-blocks of the partitioned DFT CODEC circuitry within the IC design based on the locations of end points within the scan chains and the assigned scan chains.

11 . The system of claim 10 , wherein the instructions further cause the processor to cluster the scan chains based on the location of the end points, wherein the scan chains are assigned to each of the two or more sub-blocks based on the clustering.

12 . The system of claim 10 , wherein the instructions further cause the processor to partition the DFT CODEC circuitry into four, eight, or sixteen pairs of compressor-decompressor sub-blocks.

13 . The system of claim 10 , wherein the instructions further cause the processor to partition the DFT CODEC circuitry by determining that each of the two or more sub-blocks are associated with a threshold number of scan chains.

14 . The system of claim 10 , wherein the instructions further cause the processor to assign the scan chains to each of the two or more sub-blocks by generating a mapping between the end points and the two or more sub-blocks.

15 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

partition a portion of an integrated circuit (IC) design that comprises Design For Testability (DFT) Compressor Decompressor (CODEC) circuitry, into two or more sub-blocks based on a number of scan chains within the IC design;

assign the scan chains to each of the two or more sub-blocks based on locations of end points within each of the scan chains; and

generate a layout of the IC design by placing the two or more sub-blocks of the partitioned DFT CODEC circuitry within the IC design based on the locations of end points within the scan chains and the assigned scan chains.

16 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to cluster the scan chains based on the location of the end points, and to assign the scan chains to each of the two or more sub-blocks based on the clustering.

17 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to cluster the scan chains based on a type, and to assign the scan chains to each of the two or more sub-blocks based on the clustering.

18 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to partition the DFT CODEC circuitry by determining that each of the two or more sub-blocks are associated with a threshold number of scan chains.

19 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to assign the scan chains to each of the two or more sub-blocks by generating a mapping between the end points and the two or more sub-blocks.

20 . The non-transitory computer readable medium of claim 15 , wherein the instructions further cause the processor to partition the DFT CODEC circuitry into four, eight, or sixteen pairs of compressor-decompressor sub-blocks.