Programmable sequence-driven hardware trigger for multiple FPGA system
Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware (“Debug FPGA”) that performs a series of Boolean evaluations according to testbench configurations loaded at runtime. FPGAs performing the DUT operate synchronously, in which each component must start, stop, and step through the DUT's operations according to the Boolean operations of the Debug FPGA. The hardware and software functions disclosed simultaneously stop the clocks of the FPGAs according to user-defined trigger conditions in the DUT output, allowing the designer to stop the prototyping system to analyze or debug the DUT. Based on the data outputs from the FPGAs performing the DUT, the Boolean expressions of the Debug FPGA detect state transitions or trigger events occurring within the DUT. When the Debug FPGA detects a trigger event, the Debug FPGA transmits a clock-stopping signal to each of the FPGAs.
1 . A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:
a debug FPGA configured to:
receive a signal pattern of data received from one or more user FPGAs performing a DUT;
identify a state transition of the DUT based upon the signal pattern from the one or more user FPGAs performing the DUT;
identify a trigger event based upon comparing the signal pattern against a trigger condition stored into a trigger mask register of the debug FPGA that is updated for each clock cycle, wherein the trigger condition is based on machine-executable testbench instructions of a configuration file; and
transmit a trigger signal to the one or more user FPGAs for stopping a clock of the one or more user FPGAs in response to identifying the trigger event.
2 . The system according to claim 1 , wherein the debug FPGA is further configured to:
identify a master FPGA of the one or more user FPGAs based upon a destination indicator of a master mask register,
wherein the debug FPGA transmits the trigger signal to the master FPGA of the one or more user FPGAs.
3 . The system according to claim 1 , further comprising:
a debug interface module coupled to the debug FPGA, configured to:
receive one or more data packets containing a data output from the one or more user FPGAs; and
convert the one or more data packets into the signal pattern.
4 . The system according to claim 1 , wherein the debug FPGA receives a plurality of signal patterns containing a plurality of corresponding data from the one or more user FPGAs, and
wherein the debug FPGA receives each signal pattern at a corresponding clock cycle of the DUT performed by the one or more user FPGAs.
5 . The system according to claim 1 , wherein the debug FPGA includes one or more logic devices organized as one or more hardware nodes, each hardware node configured to perform a Boolean operation according to testbench instructions compiled from testbench code for identifying the trigger event.
6 . The system according to claim 5 , wherein the debug FPGA is further configured to receive one or more Boolean operations for the corresponding one or more hardware nodes, the one or more Boolean operations comprising machine-executable instructions parsed from one or more configuration files for a clock cycle of the clock.
7 . The system according to claim 5 , wherein one or more bits of the trigger mask register indicate a deciding hardware node of the one or more hardware nodes, and wherein the Boolean operation of the deciding hardware node represents the trigger condition indicating the trigger event.
8 . The system according to claim 1 , wherein the debug FPGA is further configured to:
for a first clock cycle of the clock,
receive a set of one or more bits of a first trigger mask according to the machine-executable testbench instructions of the configuration file; and
store the first trigger mask into the trigger mask register; and
for a next clock cycle of the clock,
receive an updated set of one or more bits of a second trigger mask according to the machine-executable testbench instructions of the configuration file; and
store the second trigger mask into the trigger mask register.
9 . The system according to claim 1 , wherein the debug FPGA comprises an interface module configured to:
receive one or more data packets from a user FPGA; and
generate the signal pattern for the debug FPGA converted from the one or more data packets.
10 . A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:
a plurality of user FPGAs, including a set of one or more user FPGAs configured to:
receive an instruction set for performing a DUT for an IC design file; and
generate a data output based upon the instruction set for a clock cycle of a clock associated with the set of one or more user FPGAs; and
a debug FPGA configured to:
identify a trigger event based upon comparing a signal pattern for each data output from the set of one or more user FPGAs against a trigger condition stored into a trigger mask register of the debug FPGA that is updated for each clock cycle, wherein the trigger condition is based on machine-executable testbench instructions of a configuration file;
identify a master FPGA of the set of one or more user FPGAs based upon a destination indicator of a master mask register; and
transmit a trigger signal to the master FPGA of the set of one or more user FPGAs for stopping the clock at the master FPGA for the set of one or more user FPGAs.
11 . The system according to claim 10 , each debug FPGA further configured to identify a state transition of the DUT based upon the signal pattern from the set of one or more user FPGAs performing the DUT.
12 . The system according to claim 10 , wherein each user FPGA comprises a clock circuit configured to receive the trigger signal for stopping the clock of a respective user FPGA, and
wherein the clock circuit of the Master FPGA is further configured to send the trigger signal to each of the clock circuits of the set of one or more user FPGAs.
13 . The system according to claim 10 , wherein each user FPGA includes a user interface module for a respective user FPGA, the user interface module configured to:
generate one or more data packets containing the data output generated by the respective user FPGA at the clock cycle; and
transmit the one or more data packets containing the data output to the debug FPGA.
14 . The system according to claim 10 , further comprising a debug interface module coupled to the debug FPGA, the debug interface module configured to:
receive one or more data packets containing the data output from the set of one or more user FPGAs; and
convert the one or more data packets into the signal pattern for the data output from the set of one or more user FPGAs.
15 . A system for prototyping designs-under-test (DUTs) of integrated circuit (IC) designs using programmable field-programmable gate arrays (FPGAs), the system comprising:
a processor configured to:
compile a plurality of instruction sets for a DUT from an IC design file and a plurality of testbench instructions according to one or more configuration files; and
for a first clock cycle of the DUT, parse the plurality of testbench instructions for a plurality of registers of a debug FPGA; and
the debug FPGA configured to, for the first clock cycle of the DUT:
update the plurality of registers according to the plurality of testbench instructions parsed for the first clock cycle, including a trigger mask register;
identify a trigger event based upon comparing a signal pattern for data outputs from one or more user FPGAs against a trigger condition indicated by the trigger mask register, wherein the trigger condition is based on the plurality of testbench instructions of the one or more configuration files; and
transmit a trigger signal to the one or more user FPGAs for stopping a clock of the one or more user FPGAs in response to identifying the trigger event.
16 . The system according to claim 15 , wherein the debug FPGA is further configured to:
update a master FPGA register of the plurality of registers according to a destination indicator of the plurality of testbench instructions parsed for the first clock cycle; and
identify the master FPGA of the one or more user FPGAs based upon the destination indicator of a master mask register,
wherein the debug FPGA transmits the trigger signal to the master FPGA of the one or more user FPGAs.
17 . The system according to claim 15 , wherein the debug FPGA includes one or more logic devices organized as one or more hardware nodes, and wherein each hardware node is configured to perform a Boolean operation according to the plurality of testbench instructions for the first clock cycle.
18 . The system according to claim 17 , wherein one or more bits of the trigger mask register indicate a deciding hardware node of the one or more hardware nodes for the first clock cycle, and wherein the Boolean operation of the deciding hardware node represents the trigger condition indicating the trigger event for the first clock cycle.
19 . The system according to claim 15 , wherein the processor is further configured to, for a second clock cycle of the DUT, parse the plurality of testbench instructions to generate updated testbench instructions for the plurality of registers of the debug FPGA; and
wherein the debug FPGA is further configured to, for the second clock cycle of the DUT:
update the trigger mask register of the plurality of registers according to the updated testbench instructions; and
identify a second trigger event based upon comparing an updated signal pattern for updated data outputs from the one or more user FPGAs against an updated trigger condition indicated by the trigger mask register.
20 . The system according to claim 19 , wherein the debug FPGA is further configured to, for the second clock cycle:
update a master mask register of the plurality of registers according to an updated destination indicator of the updated testbench instructions; and
identify an updated master FPGA of the one or more user FPGAs based upon the updated destination indicator of the master mask register, wherein the debug FPGA transmits the trigger signal to the updated master FPGA of the one or more user FPGAs according to the updated destination indicator.