IP Library › Granted Patent US 12670308
Granted Patent B2
US 12670308 · App. 17/930,506 · Granted Jun 30, 2026

Workload aware exerciser device placement

Inventors: Michael Romain (Beacon, NY); Lucas Dane LaLima (Poughkeepsie, NY); Michael Greene (Austin, TX); Alper Buyuktosunoglu (White Plains, NY); Christopher Joseph Berry (Red Hook, NY); Pawel Owczarczyk (Highland, NY); Mark Cichanowski (Hutto, TX); William V. Huott (Holmes, NY); Ofer Geva (Poughkeepsie, NY); Jesse Peter Surprise (Highland, NY); Eduard Herkel (Stuttgart, DE)
Assignee: International Business Machines Corporation
G06F30/392G06F30/398G06F2111/04G06F2119/06
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Quick Facts
Patent No.
US 12670308
App. No.
17/930,506
Granted
Jun 30, 2026
Kind
B2
Abstract

Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.

Claims (35)

1 . A method for exerciser device placement in the development of an integrated circuit, the method comprising:

obtaining a design of an integrated circuit;

creating a dynamic power blockage map for the integrated circuit;

updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map;

based on a determination that the updated integrated circuit design complies with one or more design constraints, outputting the updated integrated circuit design; and

creating an updated dynamic power blockage map for the integrated circuit based on an exerciser having a power consumption level that is less than a power consumption level of the one or more exercisers, based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit does not include least one additional viable exercisers placement location.

2 . The method of claim 1 , wherein the dynamic power blockage map is created by applying one or more power density-based blockages for one or more workloads to the design of the integrated circuit and applying one or more resource-based blockages to the design of the integrated circuit.

3 . The method of claim 2 , wherein the dynamic power blockage map is created by further applying one or more custom blockages to the design of the integrated circuit.

4 . The method of claim 1 , wherein the dynamic power blockage map is created based on a power consumption level of the one or more exercisers.

5 . The method of claim 1 , wherein the with one or more design constraints compliance with a maximum operating voltage of the integrated circuit.

6 . The method of claim 1 , further comprising updating the integrated circuit design by placing an additional exerciser on the integrated circuit based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit includes at least one additional viable exercisers placement location.

7 . A system comprising:

a memory having computer readable instructions; and

one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:

obtaining a design of an integrated circuit;

creating a dynamic power blockage map for the integrated circuit;

updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map;

based on a determination that the updated integrated circuit design complies with one or more design constraints, outputting the updated integrated circuit design; and

creating an updated dynamic power blockage map for the integrated circuit based on an exerciser having a power consumption level that is less than a power consumption level of the one or more exercisers, based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit does not include least one additional viable exercisers placement location.

8 . The system of claim 7 , wherein the dynamic power blockage map is created by applying one or more power density-based blockages for one or more workloads to the design of the integrated circuit and applying one or more resource-based blockages to the design of the integrated circuit.

9 . The system of claim 8 , wherein the dynamic power blockage map is created by further applying one or more custom blockages to the design of the integrated circuit.

10 . The system of claim 7 , wherein the dynamic power blockage map is created based on a power consumption level of the one or more exercisers.

11 . The system of claim 7 , wherein the with one or more design constraints compliance with a maximum operating voltage of the integrated circuit.

12 . The system of claim 7 , wherein the operations further comprise updating the integrated circuit design by placing an additional exerciser on the integrated circuit based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit includes at least one additional viable exercisers placement location.

13 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:

obtaining a design of an integrated circuit;

creating a dynamic power blockage map for the integrated circuit;

updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map;

based on a determination that the updated integrated circuit design complies with one or more design constraints, outputting the updated integrated circuit design; and

creating an updated dynamic power blockage map for the integrated circuit based on an exerciser having a power consumption level that is less than a power consumption level of the one or more exercisers, based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit does not include least one additional viable exercisers placement location.

14 . The computer program product of claim 13 , wherein the dynamic power blockage map is created by applying one or more power density-based blockages for one or more workloads to the design of the integrated circuit and applying one or more resource-based blockages to the design of the integrated circuit.

15 . The computer program product of claim 14 , wherein the dynamic power blockage map is created by further applying one or more custom blockages to the design of the integrated circuit.

16 . The computer program product of claim 13 , wherein the dynamic power blockage map is created based on a power consumption level of the one or more exercisers.

17 . The computer program product of claim 13 , wherein the with one or more design constraints compliance with a maximum operating voltage of the integrated circuit.

18 . The computer program product of claim 13 , wherein the operations further comprise updating the integrated circuit design by placing an additional exerciser on the integrated circuit based on a determination that the updated integrated circuit design does not comply with one or more design constraints and that the updated design of the integrated circuit includes at least one additional viable exercisers placement location.