System and method for diagnosing design rule check violations

1 . A method comprising:

receiving, by a processor executing computer-readable instructions stored on a memory, a layout pattern having a design rule check (DRC) violation therein;

determining, by the processor, whether the layout pattern is an outlier or an inlier, based on previously corrected DRC violations;

classifying, by the processor, the DRC violation in the layout pattern based upon a pattern type, a violation type that is determined based on the pattern type, and a layer having the DRC violation that is determined based on the violation type;

selecting, by the processor, a recipe from a pool of recipes to fix the DRC violation in the layout pattern comparing, by the processor, the layout pattern with a plurality of previously analyzed layout patterns;

identifying, by the processor, based upon a classification of the DRC violation, a subset of previously analyzed layout patterns from the plurality of previously analyzed layout patterns having DRC violations that are similar to the DRC violation in the layout pattern for selecting the recipe, wherein selecting the recipe from the pool of recipes comprises determining the recipe having a highest fix rate amongst the pool of recipes, wherein the pool of recipes comprises previously applied recipes to the subset of previously analyzed layout patterns; and

manufacturing a semiconductor device based at least in part on the layout pattern.

2 . The method of claim 1 , wherein the pattern type determines whether the DRC violation is in a metal interconnect or a via structure.

3 . The method of claim 1 , wherein the violation type comprises at least one of spacing, area, length, recommended, width, overlap, enclose, color spacing, extension, or double pattern rule violation types.

4 . The method of claim 1 , wherein the layer having the DRC violation comprises one of a first group of metal interconnect layers, a second group of metal interconnect layers, or a third group of metal interconnect layers.

5 . The method of claim 1 , wherein the pool of recipes include at least one recipe previously applied to fix the DRC violation.

6 . The method of claim 1 , wherein selecting the recipe from the pool of recipes comprises ranking pattern violations in the subset of previously analyzed layout patterns, and selecting the recipe previously applied to a highest ranked pattern violation.

7 . The method of claim 1 , wherein the selecting the recipe is performed by at least one of a k-nearest neighbor classifier or a random forest classifier.

8 . The method of claim 1 , wherein anomaly detection algorithm comprises an isolation forest classifier.

9 . The method of claim 8 , further comprising changing an orientation of the layout pattern for determining that the layout pattern is an inlier.

10 . A system comprising:

a memory having computer-readable instructions stored thereon; and

a processor that executes the computer-readable instructions to:

receive a layout pattern having a design rule check (DRC) violation therein;

determine whether the layout pattern is an outlier or an inlier, based on previously corrected DRC violations;

classify the DRC violation in the layout pattern based upon a pattern type, a violation type that is determined based on the pattern type, and a layer having the DRC violation that is determined based on the violation type;

select a recipe from a pool of recipes to fix the DRC violation in the layout pattern comparing the layout pattern with a plurality of previously analyzed layout patterns;

identifying based upon a classification of the DRC violation, a subset of previously analyzed layout patterns from the plurality of previously analyzed layout patterns having DRC violations that are similar to the DRC violation in the layout pattern for selecting the recipe, wherein selecting the recipe from the pool of recipes comprises determining the recipe having a highest fix rate amongst the pool of recipes, wherein the pool of recipes comprises previously applied recipes to the subset of previously analyzed layout patterns; and

manufacture a semiconductor device based at least in part on the layout pattern.

11 . The system of claim 10 , wherein the processor further executes the computer-readable instructions to determine that the layout pattern is an inlier based upon an anomaly detection algorithm.

12 . The system of claim 10 , wherein to select the recipe from the pool of recipes, the processor further executes the computer-readable instructions to generate at least one of a pattern violation graph or a recipe fix rate graph, wherein the pattern violation graph identifies pattern violations identified in a group of previously analyzed layout patterns, and wherein the recipe fix rate graph identifies a fix rate of each recipe in the pool of recipes.

13 . The system of claim 12 , wherein the processor further executes the computer-readable instructions to select the recipe having a highest fix rate in the recipe fix rate graph as the recipe.

14 . The system of claim 12 , wherein the processor further executes the computer-readable instructions to:

rank the pattern violations in the pattern violation graph; and

select the recipe previously applied to a highest ranked pattern violation as the recipe.

15 . A non-transitory computer-readable media comprising computer-readable instructions stored thereon, that when executed by a processor cause the processor to:

receive a layout pattern having a design rule check (DRC) violation therein;

determine whether the layout pattern is associated with previously corrected DRC violations;

classify the DRC violation in the layout pattern based upon a pattern type, a violation type that is determined based on the pattern type, and a layer having the DRC violation that is determined based on the violation type;

select a recipe from a pool of recipes to fix the DRC violation in the layout pattern compare the layout pattern with a plurality of previously analyzed layout patterns;

identify based upon a classification of the DRC violation, a subset of previously analyzed layout patterns from the plurality of previously analyzed layout patterns having DRC violations that are similar to the DRC violation in the layout pattern for selecting the recipe, wherein selecting the recipe from the pool of recipes comprises determining the recipe having a highest fix rate amongst the pool of recipes, wherein the pool of recipes comprises previously applied recipes to the subset of previously analyzed layout patterns; and

manufacture a semiconductor device based at least in part on the layout pattern.

16 . The non-transitory computer-readable media of claim 15 , further comprising determining that the layout pattern is an inlier before classifying the DRC violation in response to a determination that the layout pattern is associated with the previously corrected DRC violations.

17 . The non-transitory computer-readable media of claim 15 , wherein the pattern type determines whether the DRC violation is in a metal interconnect or a via structure.

18 . The non-transitory computer-readable media of claim 15 , wherein the violation type comprises at least one of spacing, area, length, recommended, width, overlap, enclose, color spacing, extension, or double pattern rule violation types.

19 . The non-transitory computer-readable media of claim 15 , wherein the layer having the DRC violation comprises one of a first group of metal interconnect layers, a second group of metal interconnect layers, or a third group of metal interconnect layers.

20 . The non-transitory computer-readable media of claim 15 , wherein the pool of recipes include at least one recipe previously applied to fix the DRC violation.