Testing circuitry and methods for analog neural memory in artificial neural network
In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where Nis a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.
1 . A method comprising:
programming a first group of analog neural non-volatile memory cells in a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells with a level corresponding to the smallest cell current among N levels, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells and where the plurality of analog neural non-volatile memory cells is fewer than all of the analog neural non-volatile memory cells in the array;
programming a second group of analog neural non-volatile memory cells in the plurality of analog neural non-volatile memory cells with a level corresponding to the largest cell current among the N levels, wherein each of the analog neural non-volatile memory cells in the second group is adjacent within the array to one or more of the analog neural non-volatile memory cells in the first group, thereby generating the highest electrical field possible among all combinations of the N levels in adjacent cells;
measuring a current drawn by the first group and the second group of analog neural non-volatile memory cells;
comparing the measured current to a target value; and
identifying the plurality of analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.
2 . The method of claim 1 , wherein the plurality of analog neural non-volatile memory cells are stacked-gate flash memory cells.
3 . The method of claim 1 , wherein the plurality of analog neural non-volatile memory cells are split-gate flash memory cells.
4 . The method of claim 1 , wherein the plurality of analog neural non-volatile memory cells are part of a neural network.
5 . A system comprising:
a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells; and
test control logic to perform a checkerboard verification test comprising:
programming a first group of analog neural non-volatile memory cells in a plurality of analog neural non-volatile memory cells with a level corresponding to the smallest cell current among N levels, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells and where the plurality of analog neural non-volatile memory cells is fewer than all of the analog neural non-volatile memory cells in the array;
programming a second group of analog neural non-volatile memory cells in the plurality of analog neural non-volatile memory cells with a level corresponding to the largest cell current among the N levels, wherein each of the analog neural non-volatile memory cells in the second group is adjacent within the array to one or more of the analog neural non-volatile memory cells in the first group, thereby generating the highest electrical field possible among all combinations of the N levels in adjacent cells;
measuring a current drawn by the first group and the second group of analog neural non-volatile memory cells;
comparing the measured current to a target value; and
identifying the plurality of analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.
6 . The system of claim 5 , wherein the plurality of analog neural non-volatile memory cells are stacked-gate flash memory cells.
7 . The system of claim 5 , wherein the plurality of analog neural non-volatile memory cells are split-gate flash memory cells.
8 . The system of claim 5 , wherein the plurality of analog neural non-volatile memory cells are part of a neural network.