IP Library Granted Patent US 12670378
Granted Patent B2
US 12670378 · App. 18/736,611 · Granted Jun 30, 2026

Memristor structures with analog switching characteristics and method for fabricating the same

Inventors: Ngoc Kim Pham (Di An, VN); Quan Phu Pham (Ho Chi Minh, VN); Thang Bach Phan (Ho Chi Minh, VN); Thuat Tran Nguyen (Ha Noi, VN)
Assignee: VNUHCM-University of Science
G06N3/065H10N70/026H10N70/24H10N70/841H10N70/8833
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Quick Facts
Patent No.
US 12670378
App. No.
18/736,611
Granted
Jun 30, 2026
Kind
B2
Abstract

A method for fabricating a memristor and a memristor device are disclosed which comprises: depositing a first metal electrode on a substrate; depositing a Chromium oxide (CrO x ) layer directly on top of a first metal electrode; depositing a Titanium oxide (TiO y ) layer directly on top of the CrO x layer; and depositing a second metal electrode on the TiO y layer.

Claims (35)

1 . A method for fabricating a memristor device, comprising:

(a) depositing a first metal electrode on a substrate using a physical vapor deposit (PVD) sputtering method at the room temperature, wherein said first metal electrode has a dog bone shape and a first terminal and a second terminal;

(b) depositing a amorphous Chromium oxide (CrO x ) layer directly on top and on a middle section of said first metal electrode using said physical vapor deposit (PVD) sputtering method with Chromium (Cr) having a purity of 99.95%;

(c) depositing a Titanium oxide (TiO y ) layer directly on top of said amorphous CrO x layer using said physical vapor deposit (PVD) sputtering method with Titanium (Ti) vapor having a purity of 99.2%-99.7%; and

(d) depositing a second metal electrode directly on said TiO y layer using said physical vapor deposit (PVD) sputtering method; wherein said second metal electrode has a dog bone shape and a third terminal and a fourth terminal, said second metal electrode is deposited perpendicular to said first metal electrode; and said first terminal, said second terminal, said third terminal, and said fourth terminal are extended beyond the edges of said amorphous Chromium oxide (CrO x ) layer and said Titanium oxide (TiO y ) layer so that said memristor device is characterized by having a multi-functional capabilities of a Schottky Barrier diode, a non-linear capacitor, and a nonvolatile analog memory.

2 . The method of claim 1 wherein said dog bone shape of said first metal electrode comprises a connective strip with a width of 500 μm and said first terminal and said second terminal have a 1.5 mm×1.5 mm square shape.

3 . The method of claim 1 wherein said first metal electrode comprises Titanium (Ti), wherein said Schottky Barrier diode comprises a first Schottky barrier diode which is formed between said first metal electrode and said amorphous CrOx layer.

4 . The method of claim 3 wherein said Titanium (Ti) electrode has a thickness of 50 nm to 150 nm, preferably 70 nm.

5 . The method of claim 4 wherein said second metal electrode comprises Chromium (Cr), wherein said Schottky Barrier diode comprises a second Schottky barrier diode which is formed between said second metal electrode and said TiOy layer.

6 . The method of claim 5 wherein said Chromium (Cr) electrode has a thickness of 50 nm to 150 nm, preferably 70 nm.

7 . The method of claim 1 wherein said substrate is a glass substrate.

8 . The method of claim 1 wherein said step (a) of depositing a first metal electrode on a substrate comprises said physical vapor deposit (PVD) method that uses a DC sputtering of Argon (Ar) gas in a vacuum chamber set at a working pressure of 3×10 −3 Torr with a base vacuum pressure of 7.5×10 −6 Torr.

9 . The method of claim 8 wherein electrodes of said vacuum chamber is applied a power of 100 W for 5 minutes.

10 . The method of claim 9 wherein said physical vapor deposit (PVD) method comprises a reactive sputtering deposition that uses Argon (Ar) and Oxygen (O 2 ) gases in a vacuum chamber set at a pressure of 7×10 −3 Torr with a base vacuum pressure of 7.5×10 −6 Torr.

11 . The method of claim 10 wherein said dog bone shape of said Chromium (Cr) electrode comprises a connective strip with a width of 500 μm and said third terminal and said fourth terminal have a 1.5 mm×1.5 mm square shape.

12 . The method of claim 11 wherein said CrOx layer has a thickness of 130 nm.

13 . The method of claim 12 wherein said TiOy layer has a thickness of 160 nm.

14 . A memristor device, comprising:

a first metal electrode deposited on a glass substrate, wherein said first metal electrode has a dog bone shape and a first terminal and a second terminal;

a 99.95% Chromium (Cr) in an amorphous Chromium oxide (CrO x ) layer deposited directly on top of and on a middle of said first metal electrode;

a 99.2%-99.7% Titanium in a Titanium oxide (TiO y ) layer deposited directly on top of said CrO x layer; and

a second metal electrode formed directly on said TiO y layer; wherein said second metal electrode has a dog bone shape and a third terminal and a fourth terminal; said second metal electrode is deposited perpendicular to said first metal electrode; and said first terminal, said second terminal, said third terminal, and said terminal are extended beyond the edges of said amorphous Chromium oxide (CrO x ) layer and said Titanium oxide (TiO y ) layer; wherein said memristor device is characterized by having a multi-functional capabilities of a Schottkey barrier diode, a non-linear capacity, and a nonvolatile analog memory.

15 . The memristor device of claim 14 wherein said first metal electrode comprises Titanium (Ti), wherein said Schottky barrier diode comprises a first Schottky barrier diode which is formed between said first metal electrode and said CrOx layer.

16 . The memristor device of claim 15 wherein said Ti layer has a thickness between 50 nm to 150 nm, preferably 70 nm.

17 . The method of claim 15 wherein said second metal electrode comprises Chromium (Cr), wherein said Schottky barrier diode comprises a second Schottky barrier diode which is formed between said second metal electrode and said TiOy layer.

18 . The memristor device of claim 17 wherein said Cr layer has a thickness between 50 nm to 150 nm, preferably 70 nm.

19 . A neural network, comprising:

an input layer comprising a plurality of input neurons;

a plurality of hidden layers comprising a second plurality of processing neurons; and

an output layer comprising a plurality of output neurons, wherein said input layer, said plurality of hidden layers, and said output layers are connected together by a plurality of memristors, wherein each of said memristors further comprises:

a Titanium (Ti) electrode deposited on a glass substrate, wherein said Ti electrode has a dog bone shape and a first terminal and a second terminal;

a 99.95% Chromium (Cr) in an amorphous Chromium oxide (CrO x ) layer directly on top of and on a middle of said Ti electrode;

a 99.2%-99.7% Titanium in a Titanium oxide (TiO y ) layer directly on top of said CrO x layer; and

a Chromium (Cr) electrode formed directly on said TiOy layer; wherein said Cr electrode has a dog bone shape and a third terminal and a fourth terminal; said Cr electrode is deposited perpendicular to said Ti electrode; and said first terminal, said second terminal, said third terminal, and said fourth terminal are extended beyond the edges of said amorphous Chromium oxide (CrO x ) and said Titanium oxide (TiO y ); wherein said memristor device is characterized by having a multi-functional capabilities comprising a Schottky barrier diode, a non-linear capacitor, and a nonvolatile analog memory.

20 . The neural network of claim 19 wherein said amorphous CrO x layer has a thickness of 130 nm, said TiO y layer has a thickness of 160 nm, said first Ti electrode has a thickness of 50 nm to 100 nm, preferably 70 nm; and said second Cr electrode has a thickness of 50 nm to 150 nm, preferably 70 nm, wherein said Schottky barrier diode comprises a first Schottky barrier diode which is formed between said first metal electrode and said TiOy layer and wherein said Schottky barrier diode comprises a second Schottky barrier diode which is formed between said second metal electrode and said amorphous CrOx layer.