Apparatus for low CNOT count quantum point-doubling circuits

1 . A low controlled NOT (CNOT) count quantum point doubling circuit, comprising:

a first quantum register to which a control qubit |q is input, a second quantum register to which a quantum register value |x 1 is input, a third quantum register to which a quantum register value |y 1 is input, a first ancilla register to which |0 is input, and a second ancilla register to which |0 is input, wherein x 1 and y 1 are coordinate values indicating a point in an elliptic curve, |x 1 and |y 1 indicate quantum states thereof, and q represents a value of the input control qubit |q ; and

a division operation block configured to output a first value of the first ancilla register as

anc

1

=

y

1

x

1

,

using the quantum register values |x 1 and |y 1 .

2 . The circuit of claim 1 , further comprising a first multiplication operation block with a triple-controlled gate structure configured to output a value of y A =0, when q=1, and y A =y 1 , when q=0.

3 . The circuit of claim 2 , further comprising a CNOT gate configured to output a second value of the first ancilla register as

anc

1

=

y

1

x

1

+

x

1

=

λ

,

wherein λ mdicates a gradient having a value of

y

1

x

1

+

x

1

.

4 . The circuit of claim 3 , further comprising a controlled out-of-place squaring block configured to output a value of y B =λ 2 , when q=1, and y B =y 1 , when q=0.

5 . The circuit of claim 4 , further comprising a first Toffoli gate configured to output a value of y C =λ 2 +λ, when q=1, and y C =y 1 , when q=0.

6 . The circuit of claim 5 , further comprising a constant addition block configured to output y D =λ 2 +λ+α=x 3 , when q=1, and y D =y 1 , when q=0, wherein x 3 is a value derived from x 1 and y 1 in a point doubling calculation process, and a is a constant.

7 . The circuit of claim 6 , further comprising a first constant addition block configured to output a third value of the first ancilla register as anc 1 =λ+1.

8 . The circuit of claim 7 , further comprising a controlled in-place squaring block configured to output a first value of the second ancilla register as anc 2 =(λ+1)x 3 , when q=1, and anc 2 =(λ+1) y 1 , when q=0.

9 . The circuit of claim 8 , further comprising a second multiplication operation block configured to output a value of x A =x 1 2 , when q=1, and x A =X 1 , when q=0.

10 . The circuit of claim 9 , further comprising:

a controlled swap block configured to output swap: x B =x 3 , y D =y 3 , when q=1, and none: x B =x 1 , y D =y 1 , when q=0.

11 . The circuit of claim 10 , wherein a final output value of the first ancilla register is anc 1 =|λ+1 , and a final output value of the second ancilla register is anc 2 =|(λ+1) x 3 or anc 2 =|(λ+1) y 1 .

12 . The circuit of claim 9 , further comprising:

a third multiplication operation block configured to output a second value of the second ancilla register as anc 2 =0; and

a controlled swap block configured to output swap: x B =x 3 , y D =y 3 , when q=1, and outputs none: x B =x 1 , y D =y 1 , when q=0.

13 . The circuit of claim 11 ,

wherein a final output value of the first ancilla register is anc 1 =|λ+1 , and a final output value of the second ancilla register is anc 2 =|0 .

14 . The circuit of claim 11 , further comprising:

a second constant addition block configured to output a fourth value of the first ancilla register as anc 1 =(λ+1)−1=λ when q=1, and anc 1 =λ when q=0.

15 . The circuit of claim 13 , further comprising: a negative control Toffoli gate configured to output a fifth value of the first ancilla register as anc 1 =λ, when q=1, and

a

⁢

n

⁢

c

1

=

λ

-

x

1

=

y

1

x

1

,

when q=0; and a negative controlled division block configured to output a sixth value of the first ancilla register as anc 1 =λ, when q=1, and anc 1 =0, when q=0.

16 . The circuit of claim 14 ,

wherein a final output value of the first ancilla register is anc 1 =|1 or anc 1 =|0 , and a final output value of the second ancilla register is anc 2 =|0 .